ZR36050 Просмотр технического описания (PDF) - Unspecified

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Компоненты Описание

производитель

ZR36050

JPEG IMAGE COMPRESSION PROCESSOR

Unspecified 

ADVANCE INFORMATION

ZR36050

INT

24

RD (STATUS)

or WR (GO)

1. With the exception of the INT signal, an interrupt acknowledge cycle is identical to an internal memory access cycle.

Figure 42. Interrupt Acknowledge Timing

DINT

24

RD (Encoding)

or WR (Decoding)

1. With the exception of the DINT signal, a slave mode data transfer cycle is identical to an internal memory access cycle.

Figure 43. Slave Mode Compressed Data Transfer Timing

DREQ

DACK

RD

DATA

(DATA/CODE)

DREQ

DACK

WR

DATA

(DATA/CODE)

25

26

17

27

20

19

21

Valid Data

Figure 44. DMA Mode Compressed Data Transfer Timing (Encoding)

25

26

17

27

22

23

Valid Data

Figure 45. DMA Mode Compressed Data Transfer Timing (Decoding)

47

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