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VT8363

KT133 AMD ATHLON™ NORTH BRIDGE

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KT133 - VT8363

OVERVIEW

The KT133 / VT8363 and VT82C686A chipset is a high performance, cost-effective and energy efficient system controller for

the implementation of AGP / PCI / ISA desktop personal computer systems based on 64-bit Socket-A (AMD Athlon) processors.

Athlon

Host CPU

Address

Data

Out

In

3D

Graphics

Controller

PCLK

GCLK

AGP Bus

GCKRUN#

PCKRUN#

PCI Bus

KT133

VT8363

North Bridge

552 BGA

SUSCLK,

SUSST1#

BIOS ROM

ATA 33 / 66

USB Ports 0-3

AC97 Audio Codec AC97

MC97 Modem Codec Link

ISA Bus

RTC

Crystal

Super

South

VT82C686A

South Bridge

352 BGA

SYSCLK, SYSCLK#

INTR, NMI, SMI#, STPCLK#,

IGNNE#, FERR#, A20M#,

PWROK, INIT#, RESET#

CKE

Memory Bus

MCLK

HCLK

PCLK

SDRAM

Clock

Buffer

CPUSTP#

PCISTP#

SMBus

Clock

Generator

Power Plane & Peripheral Control

GPIO and ACPI Events

Hardware Monitoring Inputs

Keyboard / PS2 Mouse

Serial Ports 1 and 2

Parallel Port

Floppy Drive Interface

MIDI / Game Ports

Figure 1. KT133 System Block Diagram Using the VT82C686A South Bridge

The KT133 chip set consists of the VT8363 system controller (552 pin BGA) and the VT82C686A PCI to ISA bridge (352 pin

BGA). The system controller provides superior performance between the CPU, DRAM, AGP bus, and PCI bus with pipelined,

burst, and concurrent operation.

The VT8363 supports eight banks of DRAMs up to 1.5 GB. The DRAM controller supports standard Synchronous DRAM

(SDRAM) and Virtual Channel SDRAM (VC SDRAM), in a flexible mix / match manner. The Synchronous DRAM interface

allows zero wait state bursting between the DRAM and the data buffers at 66/100/133 MHz. The six banks of DRAM can be

composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16M / 32MxN DRAMs.

The VT8363 system controller also supports full AGP v2.0 capability for maximum bus utilization including 1x, 2x and 4x mode

transfers, SBA (SideBand Addressing), Flush/Fence commands, and pipelined grants. An eight level request queue plus a four

level post-write request queue with thirty-two and sixteen quadwords of read and write data FIFO's respectively are included for

deep pipelined and split AGP transactions. A single-level GART TLB with 16 full associative entries and flexible CPU / AGP /

PCI remapping control is also provided for operation under protected mode operating environments. Both Windows-95 VXD and

Windows-98 / Windows 2000 miniport drivers are supported for interoperability with major AGP-based 3D and DVD-capable

multimedia accelerators.

The VT8363 supports two 32-bit 3.3 / 5V system buses (one AGP and one PCI) that are synchronous / pseudo-synchronous to the

CPU bus. The chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. Five levels

(doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation, forty-

eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for concurrent

PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line, Memory-

Preliminary Revision 1.0, May 12, 2000

-4-

Overview

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