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TB62202AFG

TOSHIBA Bi−CMOS Processor IC Silicon Monolithic

Toshiba 

TB62202AFG

2. Serial input signal functions

Input

CLK STROBE DATA RESET

×

×

H

×

H

H

×

L

H

×

×

H

×

×

H

×

×

×

L

×

×

×

×

×

×

×

H

VDDR

(Note 1) or

VMR

H

H

H

H

H

×

L

H

Operation of

TSD/ISD

L

L

L

L

L

L

L

H

(Note 2)

Action

No change in shift register.

H level is input to shift register.

L level is input to shift register.

Shift register data are latched.

Qn

Output off, charge pump halted

(S/R DATA CLR)

Output off (S/R DATA CLR)

Charge pump halted

Mixed decay timing table cleared (only VDDR)

Output off (S/R DATA HOLD)

Charge pump halted

Restored when RESET goes from Low to High

×:

Don’t Care

Qn: Latched output level when STROBE is .

Note 1: VDDR and VMR

H when the operable range (3 V typical) or higher and L when lower.

When one of VDDR or VMR is operating, the system resets (OR relationship).

Note 2: High when TSD is in operation.

When one of TSD or ISD is operating, the system resets (OR relationship).

Note: Function of overcurrent protection circuit

Until the RESET signal is input after ISD is triggered, the overcurrent protection circuit remains in operation.

During ISD, the charge pump stays halted.

When TSD and ISD are operating, the charge pump halts.

3. PHASE functions

Input

H

L

Function

Positive polarity (A: H, Α : L)

Negative polarity (A: L, Α : H)

11

2005-04-04

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