GTLP18T612MEA Просмотр технического описания (PDF) - Fairchild Semiconductor

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GTLP18T612MEA

18-Bit LVTTL/GTLP Universal Bus Transceiver

Fairchild Semiconductor 

Truth Table (Note 1)

CEAB

X

L

L

X

X

L

L

H

OEAB

H

L

L

L

L

L

L

Inputs

LEAB

X

L

L

H

H

L

L

L

L

CLKAB

X

H or L

H or L

X

X

↑

↑

X

Output

B

A

Mode

X

Z

Latched

X B0 (Note 2)

storage

X B0 (Note 3) of A data

L

L

Transparent

H

H

L

L

Clocked

H

H

storage

of A data

X B0 (Note 3) Clock inhibit

Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.

Note 2: Output level before the indicated steady state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.

Note 3: Output level before the indicated steady-state input conditions were established.

Logic Diagram

3

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