KSZ8862-100FX-EVAL Просмотр технического описания (PDF) - Micrel

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KSZ8862-100FX-EVAL

2-Port Ethernet Switch with Non-PCI Interface and Fiber Support

Micrel 

Micrel, Inc.

KSZ8862-16/32MQL

Pin Description for KSZ8862-16MQL (8/16-Bit)

Pin

Number

1

Pin Name

TEST_EN

2

SCAN_EN

3

P1LED2

4

P1LED1

5

P1LED0

Type

I

I

Opu

Opu

Opu

Pin Function

Test Enable

For normal operation, 1K ohm pull-down this pin to ground.

Scan Test Scan MUX Enable

For normal operation, 1K ohm pull-down this pin to ground.

Port 1 and Port 2 LED indicators1 defined as follows:

Switch Global Control Register 5:

SGCR5 bit [15,9]

P1LED32 /P2LED3

[0,0] Default

[0,1]

—

—

P1LED2/P2LED2

Link/Act

100Link/Act

P1LED1/P2LED1

Full duplex/Col 10Link/Act

P1LED0/P2LED0

Speed

Full duplex

Reg. SGCR5 bit [15,9]

[1,0]

P1LED32 /P2LED3

Act

[1,1]

—

P1LED2/P2LED2

Link

—

P1LED1/P2LED1

Full duplex/Col —

P1LED0/P2LED0

Speed

—

Notes:

6

P2LED2

Opu

1. Link = On; Activity = Blink; Link/Act = On/Blink; Full Dup/Col = On/Blink;

7

P2LED1

Opu

Full Duplex = On (Full duplex); Off (Half duplex)

8

P2LED0

Opu

Speed = On (100BASE-T); Off (10BASE-T)

2. P1LED3 is pin 27. P2LED3 is pin 22.

9

DGND

10

VDDIO

11

RDYRTNN

12

BCLK

13

NC

14

NC

15

SRDYN

August 2010

Gnd

Digital ground

P

3.3V digital VDDIO input power supply for IO with well decoupling capacitors.

Ipd

Ready Return Not:

For VLBus-like mode: Asserted by the host to complete synchronous read cycles. If

the host doesn’t connect to this pin, assert this pin.

For burst mode (32-bit interface only): Host drives this pin low to signal waiting

states.

Ipd

Bus Interface Clock

Local bus clock for synchronous bus systems. Maximum frequency is 50MHz.

This pin should be tied Low or unconnected if it is in asynchronous mode.

Ipu

No connect.

Opu

No connect.

Opu

Synchronous Ready Not

Ready signal to interface with synchronous bus for both EISA-like and VLBus-like

extended accesses.

For VLBus-like mode, the falling edge of this signal indicates ready. This signal is

synchronous to the bus clock signal BCLK.

For burst mode (32-bit interface only), the KSZ8862M drives this pin low to signal

wait states.

12

M9999-081310-3.1

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