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AS3588AP Просмотр технического описания (PDF) - austriamicrosystems AG

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AS3588AP
AmsAG
austriamicrosystems AG AmsAG
AS3588AP Datasheet PDF : 15 Pages
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Data Sheet
AS3588A
Read Timing Characteristics (Continued): Operation over recommended temperature and voltage range
Symbol
tSCDRD
tHCDRD
tSASRD
tHASRD
Parameter
Condition
C/D Setup Time to Read
Pulse Start
C/D Hold Time from Read
PulseEnd
Address Select Setup Time
to Read Pulse Start
Address Select Hold Time
from Read Pulse End
Min.
20
25
20
25
Typ.*
Max.
Units
ns
ns
ns
ns
tPDD
Data Delay Time
CL = 200pF
120
ns
tHZ
Delay Time to High Z
80
ns
Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing
Note: Because of internal clock re-synchronization, one single additional requirement is recommended in order to produce a
simultaneous instruction flow in a multi-chip configuration: The RD rising edge has to be 20 to 20 + tWL(CK) ns late relative to
clock falling edge.
tFRD
tRRD
RD
tWLRD
tSHRD
WR
tWHRD
tHHRD
tREPRD
CS1, CS2
tSLCSRD
tSHCSRD
tHLCSRD
tHCDRD
C/D
tSCDRD
A1=S1
A2=S2
tSASRD
tPDD
tHASRD
tHZ
DOUT
Figure 7 Read Timing
tHHCSRD
Rev. 3.1
Page 14 of 15
July 1999

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