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AD8313ARM
(Rev.:1999)

0.1 GHz-2.5 GHz/ 70 dB Logarithmic Detector/Controller

Analog Devices 

AD8313

With Pins 7 and 8 disconnected (controller mode), the output

may be stated as

VOUT v VS

VOUT v 0

when

when

VSLOPE (PIN + 100) > VSET

VSLOPE (PIN + 100) < VSET

when the input is stated in terms of the power of a sinusoidal

signal across a net termination impedance of 50 Ω. The transi-

tion zone between high and low states is very narrow, since the

output stage behaves essentially as a fast integrator. The above

equations may be restated as

VOUT v VS when VSLOPE log (VIN/2.2 µV) > VSET

VOUT v 0 when VSLOPE log (VIN/2.2 µV) < VSET

A further use of the separate VOUT and VSET pins is in raising

the load-driving current capability by the inclusion of an ex-

ternal NPN emitter follower. More complete information about

usage in these various modes is provided in the Applications

section.

VPOS 1

0.5pF

INHI 2

INLO 3

~0.75V

2.5k⍀ 2.5k⍀

0.7pF

125⍀ 125⍀

1.25k⍀

TO STAGES

1 THRU 4

TO 2ND

STAGE

0.5pF

VPOS 4

1.25k⍀

(1ST DETECTOR)

250⍀

GAIN BIAS

1.24V

~1.4mA

COMM

Figure 23. Input Interface Simplified Schematic

For high frequency use, Figure 24 shows the input impedance

plotted on a Smith chart. This measured result of a typical de-

vice includes a 191 mil 50 Ω trace and a 680 pF capacitor to

ground from the INLO pin.

INTERFACES

This section describes the signal and control interfaces and their

behavior. On-chip resistances and capacitances exhibit varia-

tions of up to ± 20%. These resistances are sometimes tempera-

ture dependent and the capacitances may be voltage dependent.

Power-Down Interface, PWDN

The power-down threshold is accurately centered at the midpoint

of the supply as shown in Figure 22. If Pin 5 is left unconnected or

tied to the supply voltage (recommended) the bias enable cur-

rent is shut off, and the current drawn from the supply is pre-

dominately through a nominal 300 kΩ chain (20 µA at 3 V). When

grounded, the bias system is turned on. The threshold level is

accurately at VPOS/2. The input bias current at the PWDN pin

when operating in the device “ON” state is approximately

5 µA for VPOS = 3 V.

VPOS 4

75k⍀

PWDN 5

50k⍀

150k⍀

TO BIAS

ENABLE

150k⍀

Frequency R +j X

100MHz 650 –j 400

900MHz 55 –j 135

1.9GHz 22 –j 65

2.5GHz 23 –j 43

AD8313 MEASURED

2.5GHz

1.9GHz

100MHz

900MHz

900⍀

1.1pF

Figure 24. Typical Input Impedance

Logarithmic/Error Output, VOUT

The rail-to-rail output interface is shown in Figure 25. VOUT

can run from within about 50 mV of ground, to within about

100 mV of the supply voltage, and is short-circuit safe to either

supply. However, the sourcing load current ISOURCE is limited by

that provided by the PNP transistor, to typically 400 µA. Larger

load currents can be provided by adding an external NPN tran-

sistor (see Applications). The dc open-loop gain of this amplifier

is high, and it may be regarded essentially as an integrator hav-

ing a capacitance of 2 pF (CINT) driven by the current-mode

signals generated by the summed outputs of the nine detector

stages, which is scaled approximately 4.0 µA/dB.

COMM 6

1 VPOS

Figure 22. Power-Down Threshold Circuitry

Signal Inputs, INHI, INLO

The simplest low frequency ac model for this interface consists

of just a 900 Ω resistance RIN in shunt with a 1.1 pF input ca-

pacitance, CIN connected across INHI and INLO. Figure 23

shows these distributed in the context of a more complete sche-

matic. The input bias voltage shown is for the enabled chip;

when disabled, it will rise by a few hundred millivolts. If the

input is coupled via capacitors, this change may cause a low-

level signal transient to be introduced, having a time-constant

formed by these capacitors and RIN. For this reason, large-

valued coupling capacitors should be well matched; this is not

necessary when using the small capacitors found in many im-

pedance transforming networks used at high frequencies.

FROM

SET-POINT

SUMMED

DETECTOR

LP

OUTPUTS

LM

BIAS

gm STAGE

CINT

ISOURCE

400␮A

VOUT

8

10mA

MAX

CL

6

COMM

Figure 25. Output Interface Circuitry

Thus, for a midscale RF input of about 3 mV, which is some

40 dB above the minimum detector output, this current is

160 µA and the output changes by 8 V/µs. When VOUT is

connected to VSET, the rise and fall times are approximately

40 ns (for RL ≥ 10 kΩ). The nominal slew rate is ± 2.5 V/µs.

The HF compensation technique results in stable operation with

a large capacitive load, CL, though the positive-going slew rate

will then be limited by ISOURCE/CL to 1 V/µs for CL = 400 pF.

REV. B

–9–

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