W78L801F(1999) Просмотр технического описания (PDF) - Winbond
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W78L801F Datasheet PDF : 20 Pages
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W78L801
BLOCK DIAGRAM
P1.0
Port
1
P1.7
Port 1
Latch
INT2~9
Interrupt
P3.0
Port
3
P3.7
Timer
0
Timer
1
Port 3
Latch
ACC
T1
B
T2
PSW
Stack
ALU
Pointer
Instruction
Decoder
&
Sequencer
SFR RAM
Address
256 bytes
RAM & SFR
Port 0
Latch
DPTR
Temp Reg.
PC
Incrementor
Addr. Reg.
P4.0
Port
4
P4.6
Port 4
Latch
Bus & Clock
Controller
Oscillator
Watchdog
Timer
Reset Block
Power control
Port 2
Latch
ALE
XTAL1 XTAL2
PSEN RST
VCC Vss
P0.0
Port
0
P0.7
P2.0
Port
2
P2.7
FUNCTIONAL DESCRIPTION
The W78L801 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, two timer/counters. The processor supports 111 different
opcodes and references both a 64K program address space and a 64K data storage space.
Timers 0, 1
Timers 0, 1 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1
and TH1 for Timer 1. The TCON and TMOD registers provide control functions for timers 0 and 1.
The operations of Timer 0 and Timer 1 are the same as in the W78C51.
I/O Port Options
The Port 0 and Port 3 of W78L801 may be configured with different types by setting the bits of the
Port Options Register POR that is located at 86H. The pins of Port 0 can be configured with either the
open drain or standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional
-4-
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