W78M032A24PL Просмотр технического описания (PDF) - Winbond
Номер в каталоге
Компоненты Описание
Список матч
W78M032A24PL Datasheet PDF : 18 Pages
| |||
W78L32/W78L032A/W78M032A
Data Read Cycle
PARAMETER
ALE Low to RD Low
SYMBOL
TDAR
MIN.
3 TCP-∆
RD Low to Data Valid
TDDA
-
Data Hold after RD High
TDDH
0
Data Float after RD High
TDDZ
0
RD Pulse Width
TDRD
6 TCP-∆
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
TYP.
-
-
-
-
6 TCP
MAX.
3 TCP+∆
4 TCP
2 TCP
2 TCP
-
UNIT
nS
nS
nS
nS
nS
NOTES
1, 2
1
2
Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
TDAW
TDAD
TDWD
TDWR
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
MIN.
3 TCP-∆
1 TCP-∆
1 TCP-∆
6 TCP-∆
TYP.
-
-
-
6 TCP
MAX.
3 TCP+∆
-
-
-
UNIT
nS
nS
nS
nS
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
TPDH
TPDA
MIN.
1 TCP
0
1 TCP
TYP.
-
-
-
MAX.
-
-
-
UNIT
nS
nS
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
- 11 -
Publication Release Date: March 7, 2006
Revision A5
Share Link: 