V53C806H50 Просмотр технического описания (PDF) - Mosel Vitelic, Corp
Номер в каталоге
Компоненты Описание
Список матч
V53C806H50 Datasheet PDF : 18 Pages
| |||
MOSEL VITELIC
has no effect on any data stored in the output latch-
es. A WE low level can also disable the output driv-
ers. During a Write cycle, if WE goes low at a time
when the CAS is low, it is necessary to use OE to
disable the output drivers prior to the WE low tran-
sition to allow Data In Setup Time (tDS) to be satis-
fied.
To retain data, 1024 Refresh Cycles are required
in each 16 ms period. There are two ways to refresh
the memory:
1. By clocking each of the 1024 row addresses
(A0 through A9) with RAS at least once every
16 ms. Any Read, Write, Read-Modify-Write or
RAS-only cycle refreshes the addressed row.
2. Using a CAS-before-RAS Refresh Cycle. If
CAS makes a transition from low to high to low
after the previous cycle and before RAS falls,
CAS-before-RAS refresh is activated. The
V53C806H uses the output of an internal
10-bit counter as the source of row addresses
and ignore external address inputs.
CAS-before-RAS is a “refresh-only” mode and no
data access or device selection is allowed. Thus,
the output remains in the High-Z state during the cy-
cle. A CAS-before-RAS counter test mode is provid-
ed to ensure reliable operation of the internal
refresh counter.
Data Retention Mode
The V53C806H offers a CMOS standby mode
that is entered by causing the RAS clock to swing
between a valid VIL and an “extra high” VIH within
0.2 V of VCC. While the RAS clock is at the extra
high level, the V53C806H power consumption is re-
duced to the low ICC6 level. Overall ICC consump-
tion when operating in this mode can be calculated
as follows:
I = (---t--R----C----)---´-----(--I--C----C----1---)---+-----(---t--R---X-----–-----t-R----C----)----´----(---I--C----C---6---)-
tRX
Where: tRC = Refresh Cycle Time
tRX = Refresh Interval/1024
V53C806H
Power-On
After application of the VCC supply, an initial
pause of 200 ms is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement of
the V53C806H is dependent on the input levels of
RAS and CAS. If RAS is low during Power-On, the
device will go into an active cycle and ICC will exhibit
current transients. It is recommended that RAS and
CAS track with VCC or be held at a valid VIH during
Power-On to avoid current surges.
Table 1. V53C806H Data Output
Operation for Various Cycle Types
Cycle Type
I/O State
Read Cycles
Data from Addressed
Memory Cell
CAS-Controlled Write
Cycle (Early Write)
High-Z
WE-Controlled Write
Cycle (Late Write)
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write
Cycles
Data from Addressed
Memory Cell
Fast Page Mode Read
Data from Addressed
Memory Cell
Fast Page Mode Write Cycle High-Z
(Early Write)
Fast Read-Modify-Write
Cycle
Data from Addressed
Memory Cell
RAS-only Refresh
High-Z
CAS-before-RAS
Refresh Cycle
Data remains as in previous
cycles
CAS-only Cycles
High-Z
V53C806H Rev. 1.6 April 1998
15
Share Link: 