U631H256 Просмотр технического описания (PDF) - Simtek Corporation

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U631H256

SoftStore 32K x 8 nvSRAM

Simtek Corporation 

U631H256

Write Cycle #1: W-controlledj

Ai

E

W

DQi

Input

DQi

Output

tcW (12)

Address Valid

tsu(E) (17)

th(A) (21)

tsu(A)

(15)

tsu(A-WH) (16)

tw(W) (13)

tsu(D) (19)

th(D) (20)

tdis(W)

Previous Data

Input Data Valid

(22)

ten(W) (23)

High Impedance

Write Cycle #2: E-controlledj

Ai

E

W

DQi

Input

DQi

Output

tsu(A)

(15)

tcW (12)

Address Valid

tw(E) (18)

th(A) (21)

tsu(W) (14)

tsu(D) (19)

th(D) (20)

Input Data Valid

High Impedance

undefined

L- to H-level

H- to L-level

i: If W is low and when E goes low, the outputs remain in the high impedance state.

j: E or W must be > VIH during address transitions.

STK Control #ML0043

6

Rev 1.1

August 15, 2006

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