CS5513-BS Просмотр технического описания (PDF) - Cirrus Logic

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CS5513-BS

16-bit and 20-bit, 8-pin ∆Σ ADC

Cirrus Logic 

CS5510/11/12/13

SWITCHING CHARACTERISTICS - CS5510/12

(TA = 25° C; V+ = 5 V ±5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; CL = 50 pF)

Parameter

Symbol Min Typ Max Unit

Master Clock Timing

Master Clock Frequency (CS5510)

Master Clock Frequency (CS5512)

Master Clock Duty Cycle

Rise Times

Fall Times

Serial Port Timing

Serial Clock Frequency (CS5510)

Serial Clock Frequency (CS5512)

SCLK High to Enter Sleep

SCLK Low to Exit Sleep

Serial Clock

SDO Read Timing

CS to Data Valid

SCLK Falling to New Data Bit

CS Rising to SDO Hi-Z

CS Falling to SCLK Rising

(Note 20) SCLK

(Note 20) SCLK

(Note 21) trise

CSB

SCLK

SDO

(Note 21) tfall

CSB

SCLK

SDO

10 32.768 130 kHz

10 32.768 200 kHz

40

-

60

%

-

-

1.0 µs

-

-

10 µs

-

50

-

ns

-

-

1.0 µs

-

-

10 µs

-

50

-

ns

(Note 22) SCLK

(Note 22) SCLK

(Note 22)

(Note 22)

Pulse Width High

Pulse Width Low

tSLP

tWAKE

t1

t2

10 32.768 130 kHz

10 32.768 200 kHz

200

- 2000 µs

10

-

-

µs

2

-

60 µs

2

-

60 µs

t3

-

-

150 ns

t4

-

-

150 ns

t5

-

-

150 ns

t11

200

-

-

ns

Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or

200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded

linearity specifications, as shown in Figures 14 and 15.

21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

22. On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as

well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for tSLP or longer,

the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for tWAKE or

longer.

DS337F3

7

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