CS5510(2000) Просмотр технического описания (PDF) - Cirrus Logic
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CS5510 Datasheet PDF : 26 Pages
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CS5510/11/12/13
SWITCHING CHARACTERISTICS - CS5511/13 (TA = 25° C; V+ = 5 V ±5%; V- = 0 V; Input
Levels: Logic 0 = 0 V, Logic 1 = V+; CL = 50 pF)
Parameter
Symbol Min Typ Max Unit
Internal Oscillator Timing
Internal Oscillator Frequency
Internal Oscillator Drift Over Temperature
Serial Port Timing
Serial Clock Frequency
SCLK High to Enter Sleep
SCLK Low to Exit Sleep
Rise Times
Fall Times
Serial Clock
SDO Read Timing
CS to Data Valid
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z
CS Falling to SCLK Rising
(Note 23) fosc
-
32
64 100 kHz
- -0.02 - %/°C
(Note 24) SCLK -
(Notes 24 and 25) tSLP 200
(Notes 24 and 25) tWAKE 10
(Note 26) trise
CSB
-
SCLK
-
SDO
-
(Note 26) tfall
CSB
-
SCLK
-
SDO
-
Pulse Width High t6
200
Pulse Width Low t7
200
t8
-
t9
-
t10
-
t11
200
-
2 MHz
- 2000 µs
-
-
µs
-
1.0 µs
-
10 µs
50
-
ns
-
1.0 µs
-
10 µs
50
-
ns
-
-
ns
-
-
ns
-
150 ns
-
150 ns
-
150 ns
-
-
ns
Notes: 23. The internal oscillator in the CS5511/13 provides the master clock for performing conversions. Data is
retrieved from the serial port using the SCLK input pin.
24. The minimum SCLK rate for the CS5511/13 assumes that SCLK is logic 0 when idle. When data is being
read from the ADC, SCLK must be burst at a minimum rate of 10 kHz and with a minimum of a 10
percent duty cycle. Rates slower than this can potentially put the ADC into sleep as the sleep mode is
entered after SCLK is logic 1 for tSLP time.
25. On the CS5511/13, the serial clock (SCLK) is used to transfer data from the CS5511/13. If SCLK is held
high (logic 1) for tSLP or longer, the CS5511/13 enters sleep mode. To exit from sleep mode, SCLK must
be held low (logic 0) for tWAKE or longer.
26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
8
DS337F1
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