CS5525-BS Просмотр технического описания (PDF) - Cirrus Logic

Номер в каталоге

Компоненты Описание

Список матч

CS5525-BS

16-Bit/20-Bit Multi-Range ADC with 4-Bit Latch

Cirrus Logic 

PIN DESCRIPTIONS

ANALOG GROUND AGND 1

POSITIVE ANALOG POWER VA+ 2

DIFFERENTIAL ANALOG INPUT AIN+ 3

DIFFERENTIAL ANALOG INPUT AIN- 4

NEGATIVE BIAS VOLTAGE NBV 5

LOGIC OUTPUT

A0 6

LOGIC OUTPUT

A1 7

CHARGE PUMP DRIVE CPD 8

CRYSTAL IN

XIN 9

CRYSTAL OUT XOUT 10

CS5525 CS5526

20 VREF+ VOLTAGE REFERENCE INPUT

19 VREF- VOLTAGE REFERENCE INPUT

18 CS CHIP SELECT

17 SDI SERIAL DATA INPUT

16 A3 LOGIC OUTPUT

15 A2 LOGIC OUTPUT

14 SDO SERIAL DATA OUTPUT

13 VD+ POSITIVE DIGITAL POWER

12 DGND DIGITAL GROUND

11 SCLK SERIAL CLOCK INPUT

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 9, 10.

A gate inside the chip is connected to these pins and can be used with a crystal to provide the

master clock for the device. Alternatively, an external (CMOS compatible) clock can be

supplied into the XIN pin to provide the master clock for the device.

Control Pins and Serial Data I/O

CS - Chip Select, Pin 18.

When active low, the port will recognize SCLK. When high the SDO pin will output a high

impedance state. CS should be changed when SCLK = 0.

SDI - Serial Data Input, Pin 17.

SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK.

SDO - Serial Data Output, Pin 14.

SDO is the serial data output. It will output a high impedance state if CS = 1.

SCLK - Serial Clock Input, Pin 11.

A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins

respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin

will recognize clocks only when CS is low.

A0, A1, A2, A3 - Logic Outputs, Pin 6, 7, 15, 16.

The logic states of A0-A3 mimic the states of the D20-D23 bits of the configuration register.

Logic Output 0 = AGND, and Logic Output 1 = VA+.

24

DS202F3

Share Link: