CS5525-BS Просмотр технического описания (PDF) - Cirrus Logic

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CS5525-BS

16-Bit/20-Bit Multi-Range ADC with 4-Bit Latch

Cirrus Logic 

CS5525 CS5526

CS

SCLK

SDI

Command Time

8 SCLKs

MSB

LSB

Data Tim e 24 SC LKs

(or 72 SC LKs for Set-up R egisters)

W rite Cycle

CS

SCLK

SDI

SDO

Command Time

8 SCLKs

MSB

LSB

Data Time 24 SCLKs

(or 72 SC LKs for Set-up Registers)

Read Cycle

SCLK

SDI

SDO

Command Time

8 SCLKs

td*

8 S CLKs C lear SD O Flag MSB

X IN /OW R

Clock Cycles

LSB

* td = X IN /O W R clo ck cycles fo r each conversion exce pt the

first conversion w hich w ill take XIN/OW R + 7 clock cycles

D ata Time

24 SCLKs

SDO Continuous Conversion Read (PF bit = 1)

Figure 6. Command and Data Word Timing.

DS202F3

13

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