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CS5516-ASZ

16/20-bit bridge transducer A/D conveter

Cirrus Logic 

CS5516, CS5520

should not be applied prior to the

CS5516/CS5520 being powered-up. With EXC,

F1, and F0 set to logic 0, the BX1 output will be

logic 0 (0 volts) and the BX2 output will be a

logic 1 (+5 volts).

A second method for configuring the converter

for dc excitation is by setting EXC = 1, and

pulling up BX1 (pin 12) to VD+ (pin 20)

through a resistor. This sets the converter for

use with external excitation which uses the

BX1 pin as an input to set the excitation fre-

quency. With BX1 = VD+, the external

excitation frequency is zero, or dc.

AC Bridge Excitation

AC bridge excitation involves using a clock sig-

nal to generate a square wave which repetitively

reverses the excitation polarity on the bridge. To

excite the bridge dynamically requires some type

of bridge driver external to the CS5516/CS5520

converter. This driver is driven by a square wave

clock. The source of this clock depends upon

whether the converter is set for internal excita-

tion or for external excitation. Figure 6

illustrates a sample bridge drive circuit when op-

erating in the internal AC excitation mode.

+5V

+5V

100 k

0.1 µF

+ 10 µF

0V

TP0610 6

BX2

2

10 k

-5V

7

+5V

EXC+

-5V

10 k

4

5

+5V

EXC-

-5V

MICREL

3

MIC4428 or

MIC4425

-5V

Figure 6. Sample AC Bridge Driver

Using internal excitation involves setting the

EXC bit of the configuration register to 0, and

setting the F1 and F0 bits to select the excitation

frequency for the bridge. In this mode the exci-

tation frequency is a sub-multiple of the XIN

clock frequency. The excitation clock is output

2222

from the BX1 and BX2 pins of the converter in

the form of a two-phase non-overlapping clock.

The converter is capable of demodulating this

clocked excitation. But only if the signals into

the AIN+ and VREF+ pins of the converter are

in phase with the demodulation clock inside the

converter (see Figure 7). The non-overlapping

clock signals from BX1 and BX2 are CMOS

level outputs (0 to VD+ volts) and are capable

of driving one TTL load. A buffer amplifier

MUST be used to drive the bridge.

BX1 (Out)

td

td

BX2 (Out)

Demod Clock

(Internal)

Note: The signals from the bridge into AIN+ and

VREF+ of the converter must be in phase

with the demodulation clock.

t d is 1 cycle of XIN clock.

Figure 7. Internal Excitation Clock Phasing

Whenever the internal mode is used for dynamic

bridge excitation the signals are non-overlap-

ping. The non-overlapping time is one XIN

clock cycle.

The converter can also be configured to provide

dynamic bridge excitation when operating in the

external-controlled bridge excitation mode. With

the EXC bit of the configuration register set to

logic 1, the BX1 pin becomes an input which

determines the bridge excitation frequency and

phase. BX1 should be near 50% duty cycle. The

user can select the excitation frequency with the

following restrictions. The excitation frequency

must be synchronous with the XIN frequency of

the converter and must be chosen using the fol-

lowing equation:

Fexc = (N × XIN) ⁄ 81,920

where N is an integer and lies in the range in-

cluding 1 to 160. Fexc is the desired bridge

excitation frequency. Other asynchronous fre-

DS74F21

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