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ST16C550
(Rev.:2003)

UART WITH 16-BYTE FIFO’s

Exar Corporation 

ST16C550

GENERAL DESCRIPTION

The ST16C550 provides serial asynchronous receive

data synchronization, parallel-to-serial and serial-to-

parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for

converting the serial data stream into parallel data that

is required with digital data systems. Synchronization

for the serial data stream is accomplished by adding

start and stops bits to the transmit data to form a data

character (character orientated protocol). Data integ-

rity is insured by attaching a parity bit to the data

character. The parity bit is checked by the receiver for

any transmission bit errors. The electronic circuitry to

provide all these functions is fairly complex especially

when manufactured on a single integrated silicon

chip. The ST16C550 represents such an integration

with greatly enhanced features. The ST16C550 is

fabricated with an advanced CMOS process.

The ST16C550 is an upward solution that provides 16

bytes of transmit and receive FIFO memory, instead

of 1 byte provided in the 16C450. The ST16C550 is

designed to work with high speed modems and shared

network environments, that require fast data process-

ing time. Increased performance is realized in the

ST16C550 by the larger transmit and receive FIFO’s.

This allows the external processor to handle more

networking tasks within a given time. The 4 selectable

levels of FIFO trigger provided for maximum data

throughput performance especially when operating in

a multi-channel environment. The combination of the

above greatly reduces the bandwidth requirement of

the external controlling CPU, increases performance,

and reduces power consumption.

The ST16C550 is capable of operation to 1.5Mbps

with a 24 MHz crystal or external clock input.

With a crystal of 14.7464 MHz and through a software

option, the user can select data rates up to 460.8Kbps

or 921.6Kbps.

FUNCTIONAL DESCRIPTIONS

Internal Registers

The ST16C550 provides 12 internal registers for

monitoring and control. These registers are shown in

Table 3 below. These registers function as data hold-

ing registers (THR/RHR), interrupt status and control

registers (IER/ISR), a FIFO control register (FCR),

line status and control registers, (LCR/LSR), modem

status and control registers (MCR/MSR), program-

mable data rate (clock) control registers (DLL/DLM),

and a user assessable scratchpad register (SPR).

Rev. 4.30

8

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