CS5126 Просмотр технического описания (PDF) - Cirrus Logic
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CS5126 Datasheet PDF : 32 Pages
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CDB5126
A 5 volt reference can be used provided the sup-
plies to the ADC are elevated to ± 5.3 volts. This
can be done by inserting 22 Ω resistors in series
with the regulator (U4 and U5) common leads.
Master Clock
The CS5126 requires an external 24.576 MHz
clock for a 96 kHz sample rate. A 24.576 MHz
clock oscillator module (U6) is provided. An ex-
ternal clock can also be selected by P1, via a
BNC connector. R15 is an optional 75 Ω termi-
nating resistor for the external clock BNC.
EXT
CLKIN
U6
BNC3
P1 1
0
R15 75
10
+5VA
+ C17 C15
R7
1 µF 0.1 µF
25
J4
TP15
VA+
3
CLKIN
4 NC
TP10
U1
CS5126
C9 20 VREF
C9 22 AGND
AINR
AINL
TP2
24 AINR
BNC1 TP3
19 AINL
BNC2
21 REFBUF
C10
VA-
C14 + C16
+5VL
P9
U8, U9 U7, Q9 Output
0.1 µF 1 µF
7
R16
U7
VD+
12
HOLD
14
SCLK
13
L/R
TP13
TP12
TP11
P2 0 47 k
1
P3 P4 0
1
R8, p.4 +5VL
26
2
TST
R17
47 k
R14
10 k
2
10 k
RST
6 SW7
DGND
C13
0.1 µF
R23
1k
R29
75
HOLD
BNC4
+5VL
R8
18
47 k
TST2
27
TST4
17
TST1
16
CODE
28
SLEEP
5
STBY
8
TRKL
9
TRKR
SSH1 10
TP9
TP8
P8
TP7
P8
TP6
15423
6-way DIP switch
SW1 thru SW6
11
SSH2
TP5
SDATA 15
TP14
U8, pin 14
VD-
-5VA
0.1 µF
C18
+ 1 µF
23
1
10
C11 R6
C12 C19
0.1 µF 0.1 µF
+ 1 µF
Figure 4. ADC Connections
24
DS32DB5
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