CS5126 Просмотр технического описания (PDF) - Cirrus Logic

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CS5126

16-Bit, Stereo A/D Converter for Digital Audio

Cirrus Logic 

CS5126

RST - Reset, PIN 32.

When taken low, all internal digital logic is reset. Upon returning high, a full calibration

sequence is initiated which takes 34,584,480 master clock cycles to complete.

Analog Inputs

AINL, AINR - Left and Right Channel Analog Inputs, PINS 19 and 24.

Analog input connections for the left and right input channels.

VREF - Voltage Reference, PIN 20.

The analog reference voltage which sets the analog input range. Its magnitude sets both positive

and negative full-scale.

Digital Outputs

STBY - Standby (Calibrating), PIN 5.

Indicates calibration status after reset. Remains low throughout the calibration sequence and

returns high upon completion.

SDATA - Serial Output, PIN 15.

Presents each output data bit on a falling edge of the SCLK input. Data is valid to be latched

on the rising edge of SCLK.

SSH1, SSH2 - Simultaneous Sample/Hold 1 and 2, PINS 10 and 11.

Used to control external sample/hold amplifier(s) to achieve simultaneous stereo sampling.

TRKL, TRKR - Tracking Left, Tracking Right, PINS 8 and 9.

Indicate the end of a conversion cycle. Either TRKL or TRKR falls at the end of a conversion

cycle depending on the status of L/R and which channel is to be tracked.

Analog Outputs

REFBUF - Reference Buffer Output, PIN 21.

Reference buffer output. A 0.1µF ceramic capacitor must be tied between this pin and VA-.

Miscellaneous

NC - No Connection, PIN 4.

Must be left floating for proper operation.

TST1, TST2, TST3, TST4 - Test, PINS 17, 18, 26, 27.

Allow access to the CS5126’s test functions which are reserved for factory use. Must be tied to

VD+.

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DS32F1

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