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HSP45106GM-25/883

16-Bit Numerically Controlled Oscillator

Intersil 

HSP45106/883

PARAMETER

TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS

SYMBOL NOTES

GROUP A

SUBGROUP

TEMPERATURE

(oC)

-25 (25.6MHz)

MIN MAX

UNITS

CLK Period

CLK High

CLK Low

WR Period

WR High

WR Low

Setup Time A(2:0), CS to WR

Going High

t CP

t CH

tCL

tWP

tWH

tWL

tAWS

9, 10, 11

9, 10, 11

9, 10, 11

9, 10, 11

9, 10, 11

9, 10, 11

9, 10, 11

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

39

-

ns

15

-

ns

15

-

ns

39

-

ns

15

-

ns

15

-

ns

13

-

ns

Hold Time A(2:0), CS from WR Go-

ing High

tAWH

9, 10, 11

-55 ≤ TA ≤ 125

2

-

ns

Setup Time C(15:0) to WR

Going High

tCWS

9, 10, 11

-55 ≤ TA ≤ 125

15

-

ns

Hold Time C(15:0) from WR

Going High

tCWH

9, 10, 11

-55 ≤ TA ≤ 125

1

-

ns

Setup Time WR High to CLK High

Setup Time MOD(2:0) to CLK

Going High

tWC

tMCS

Note 8

9, 10, 11

9, 10, 11

-55 ≤ TA ≤ 125

-55 ≤ TA ≤ 125

16

-

ns

15

-

ns

Hold Time MOD(2:0) from CLK Go-

ing High

tMCH

9, 10, 11

-55 ≤ TA ≤ 125

1

-

ns

Setup Time ENPOREG,

ENOFREG, ENCFREG,

ENPHAC, ENTIREG, INHOFR,

PMSEL, INITPAC, BINFMT, TEST,

PAR/SER, PACI, INITTAC to CLK

Going High

tECS

9, 10, 11

-55 ≤ TA ≤ 125

12

-

ns

Setup Time ENPOREG,

ENOFREG, ENCFREG,

ENPHAC, ENTIREG, INHOFR,

PMSEL, INITPAC, BINFMT, TEST,

PAR/SER, PACI, INITTAC from

CLK Going High

tECH

9, 10, 11

-55 ≤ TA ≤ 125

1

-

ns

CLK to Output Delay SIN(15:0),

tDO

COS(15:0), TICO

9, 10, 11

-55 ≤ TA ≤ 125

-

18

ns

CLK to Output Delay DACSTRB

tDSO

9, 10, 11

-55 ≤ TA ≤ 125

2

18

ns

Output Enable Time

tOE

Note 7

9, 10, 11

-55 ≤ TA ≤ 125

-

12

ns

NOTES:

6. AC Testing: VCC = 4.5V and 5.5V. Inputs are driven at 3.0V for Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are

made at 1.5V for both a Logic “1” and 0”. CLK is driven at 4.0V and 0V and measured at 2.0V. Output load per test load circuit with switch closed

and CL = 40pF.

7. Transition is measured at ±200mV from steady state voltage with loading as specified by test load circuit and CL = 40pF.

8. If ENOFRCTL, ENCFRACTL, ENTICTL, or ENPHREG are active, care must be taken to not violate setup and hold times to these registers when

writing data into the chip via the C(15:0) port.

3

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