Z89320 Просмотр технического описания (PDF) - Zilog

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Z89320

16-BIT DSP DIGITAL SIGNAL PROCESSOR

Zilog 

AC TIMING DIAGRAM

CK

/EI

ER//W

EXT (15:0)

EA (2:0)

/RDYE

PWW

TCY

TXVD

TEAD

TIED

TXWH

TIED

EXT Bus:

Output

TEAD

Valid

Data Out

Valid Address Out

TEAD

RDYS

RDYH

WRITE to external device timing

CK

/EI

ER//W

EXT (15:0)

EA (2:0)

/RDYE

PWW

TCY

TEAD

TIED

TXRH

TXRS

TIED

EXT Bus:

Input

Valid

Data In

Valid Address Out

TEAD

RDYS

RDYH

READ from external device timing

6

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