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74LVCH16541A

16-bit buffer/line driver (3-State)

Philips Electronics 

Philips Semiconductors

16-bit buffer/line driver; 5V tolerant I/O (3-State)

Product specification

74LVCH16541A

FEATURES

• 5 volt tolerant inputs/outputs for interfacing with 5V logic

• Wide supply voltage range of 1.2 V to 3.6 V

• Drive capability ±24mA @ 3.3V

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• MULTIBYTETM flow-through standard pin-out architecture

• Low inductance multiple power and ground pins for minimum

noise and ground bounce

• Direct interface with TTL levels

• All data inputs have bushold

• Bushold inputs eliminate the need for external pull-up resistors to

hold unused inputs

PIN CONFIGURATION

1OE1 1

1Y0 2

1Y1 3

GND 4

1Y2 5

1Y3 6

VCC 7

1Y4 8

1Y5 9

GND 10

1Y6 11

1Y7 12

48 1OE2

47 1A0

46 1A1

45 GND

44 1A2

43 1A3

42 VCC

41 1A4

40 1A5

39 GND

38 1A6

37 1A7

DESCRIPTION

The 74LVCH16541A is a high-performance, low-power, low-voltage,

Si-gate CMOS device, superior to most advanced CMOS

compatible TTL families. Inputs can be driven from either 3.3V or 5V

devices. In 3-State operation, outputs can handle 5V. These

features allow the use of these devices in a mixed 3.3V/5V

environment.

The 74LVCH16541A is a 16-bit inverting buffer/line driver with

3-State outputs. The 3-State outputs are controlled by the output

enable inputs 1OEn and 2OEn. A HIGH on nOEn causes the outputs

to assume a high impedance OFF-state.

To ensure the high impedance state during power up or power

down, OE should be tied to VCC through a pullup resistor; the

minimum value of the resistor is determined by the current-sinking

capability of the driver.

2Y0 13

2Y1 14

GND 15

2Y2 16

2Y3 17

VCC 18

2Y4 19

2Y5 20

GND 21

2Y6 22

2Y7 23

2OE1 24

36 2A0

35 2A1

34 GND

33 2A2

32 2A3

31 VCC

30 2A4

29 2A5

28 GND

27 2A6

26 2A7

25 2OE2

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns

SYMBOL

PARAMETER

CONDITIONS

SW00113

TYPICAL

tPHL/tPLH

Propagation delay

1An to 1Yn;

2An to 2Yn

CL = 50pF

VCC = 3.3V

2.7

CI

Input capacitance

5.0

VI = GND to VCC1

CPD

Power dissipation capacitance per buffer

outputs enabled

32

output disabled

5

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V;

S (CL × VCC2 × fo) = sum of outputs.

UNIT

ns

pF

pF

ORDERING INFORMATION

PACKAGES

48-Pin Plastic SSOP Type III

48-Pin Plastic TSSOP Type II

TEMPERATURE RANGE

–40°C to +85°C

–40°C to +85°C

OUTSIDE NORTH AMERICA

74LVCH16541A DL

74LVCH16541A DGG

NORTH AMERICA

VCH16541A DL

VCH16541A DGG

DWG NUMBER

SOT370-1

SOT362-1

1998 May 19

2

853-2063 19403

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