MCM6323ATS15AR Просмотр технического описания (PDF) - Motorola => Freescale
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MCM6323ATS15AR Datasheet PDF : 12 Pages
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WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM6323A–10 MCM6323A–12 MCM6323A–15
Parameter
Symbol
Min
Max
Min
Max
Min
Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Enable to End of Write
tAVAV
10
—
12
—
15
—
ns
3
tAVEL
0
—
0
—
0
—
ns
tAVEH
8
—
9
—
10
—
ns
tELEH,
8
—
9
—
10
—
ns
4, 5
tELWH
Data Valid to End of Write
tDVEH
4
—
5
—
6
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
LB, UB (BYTE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 2
(E Controlled)
tAVAV
tAVEH
tAVEL
tELEH
tELWH
tEHAX
HIGH–Z
tDVEH
DATA VALID
tEHDX
MCM6323A
8
MOTOROLA FAST SRAM
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