MCM6323ATS15AR Просмотр технического описания (PDF) - Motorola => Freescale
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MCM6323ATS15AR Datasheet PDF : 12 Pages
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WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6323A–10 MCM6323A–12 MCM6323A–15
Parameter
Symbol
Min
Max
Min
Max
Min
Max Unit Notes
Write Cycle Time
Address Setup Time
Address Valid to End of Write
Write Pulse Width
tAVAV
10
—
12
—
15
—
ns
3
tAVWL
0
—
0
—
0
—
ns
tAVWH
8
—
9
—
10
—
ns
tWLWH,
8
—
9
—
10
—
ns
tWLEH
Byte Pulse Width
tBLWH,
8
—
9
—
10
—
ns
tBLEH
Data Valid to End of Write
tDVWH
4
—
5
—
6
—
ns
Data Hold Time
tWHDX
0
—
0
—
0
—
ns
Write Low to Data High–Z
tWLQZ
0
4
0
5
0
6
ns 4, 5, 6
Write High to Output Active
tWHQX
3
—
3
—
3
—
ns 4, 5, 6
Write Recovery Time
tWHAX
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steady–state voltage.
5. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
6. This parameter is sampled and not 100% tested.
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
LB, UB (BYTE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 1
(W Controlled)
tAVAV
tAVWH
tAVWL
HIGH–Z
tWLQZ
tWLEH
tWLWH
tBLEH
tBLWH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MOTOROLA FAST SRAM
MCM6323A
7
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