MC10H016 Просмотр технического описания (PDF) - ON Semiconductor

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MC10H016

4−Bit Binary Counter

ON Semiconductor 

PE

P0

MR

CE

CP

Q0

MASTER

Q

SLAVE

P1

Q

Q

4–Bit Binary Counter Logic Diagram

Q1

MASTER

Q

SLAVE

P2

Q

Q

Q2

MASTER

Q

SLAVE

P3

Q

Q

Note that this diagram is provided for understanding of logic operation only. It should not be used for evaluation of

propagation delays as many gate functions are achieved internally without incurring a full gate delay.

Q3

Q

TC

1/2 10H109

Q0–Q3

CE

PE

LSB

MR

Tc

C

P0–P3

Q0–Q3

CE

PE

MR

Tc

C

Q0–Q3

CE

PE

MR

Tc

C

Q0–Q3

CE

PE

MR

Tc

C

Q0–Q3

FO

CE

PE

MSB

MR

Tc

C

P0–P3

1/2 10H109

P0–P3

1/2 10H109

P0–P3

1/2 10H109

P0–P3

CLOCK

÷N Counter 1 to 16 5

MC10H016 Cascaded for 5 Stage Presettable Counter

Max freq. is only OR gate delay below max when counting alone.

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