MAX534 Просмотр технического описания (PDF) - Maxim Integrated

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MAX534

+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers

Maxim Integrated 

+5V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

______________________________________________________________Pin Description

PIN

NAME

FUNCTION

1

OUTB

DAC B Voltage Output

2

OUTA

DAC A Voltage Output

3

REF

Reference-Voltage Input

4

UPO

Software-Programmable Logic Output

5

PDE

Power-Down Enable. Must be high to allow software shutdown mode.

6

LDAC

Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents

of each input latch to its respective DAC latch.

7

CLR

Clear DAC Input (active low). Driving CLR low asynchronously clears the input and DAC registers, and

sets all DAC outputs to zero.

8

DOUT

Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the rising or falling

edge of SCLK (Table 1).

9

CS

Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming commands are

executed when CS returns high.

10

SCLK

Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling (default) or rising

edge (A0 = A1 = 1, see Table 1).

11

DIN

Serial Data Input. Data is clocked in on the rising edge of SCLK.

12

DGND

Digital Ground

13

VDD

Power Supply, +4.5V to +5.5V

14

AGND

Analog Ground

15

OUTD

DAC D Voltage Output

16

OUTC

DAC C Voltage Output

6 _______________________________________________________________________________________

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