MAX5302 Просмотр технического описания (PDF) - Maxim Integrated

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MAX5302

Low-Power, 12-Bit Voltage-Output DAC with Serial Interface

Maxim Integrated 

Low-Power, 12-Bit Voltage-Output DAC

with Serial Interface

bits (C2, C1, C0), followed by the 12+1 data bits

D11...D0, S0 (Figure 4). Set the sub-bit (S0) to zero.

The 3-bit control code determines the register to be

updated and the configuration when exiting shutdown.

Figures 5 and 6 show the serial-interface timing require-

ments. The chip-select (CS) pin must be low to enable

the DAC’s serial interface. When CS is high, the inter-

face control circuitry is disabled. CS must go low at

least tCSS before the rising serial-clock (SCLK) edge to

properly clock in the first bit. When CS is low, data is

clocked into the internal shift register through the serial-

data input pin (DIN) on SCLK’s rising edge. The maxi-

mum guaranteed clock frequency is 10MHz. Data is

latched into the MAX5302 input/DAC register on CS’s

rising edge.

Figure 7 shows a method of connecting several

MAX5302s. In this configuration, the clock and the data

bus are common to all devices, and separate chip-select

lines are used for each IC.

Applications Information

Unipolar Output

For a unipolar output, the output voltage and the refer-

ence input have the same polarity. Figure 8 shows the

MAX5302 unipolar output circuit, which is also the typical

operating circuit. Table 2 lists the unipolar output

codes.

REF

MAX5302

DAC

+5V

VDD

FB

OUT

GND

Figure 8. Unipolar Output Circuit

Figure 9 illustrates a Rail-to-Rail® output. This circuit

shows the MAX5302 with the output amplifier configured

with a closed-loop gain of +2 to provide a 0V to 5V full-

scale range when a 2.5V reference is used.

Bipolar Output

The MAX5302 output can be configured for bipolar

operation using Figure 10’s circuit according to the fol-

lowing equation:

VOUT = VREF [(2NB / 4096) - 1]

where NB is the numeric value of the DAC’s binary

input code. Table 3 shows digital codes (offset binary)

and the corresponding output voltage for Figure 10’s

circuit.

Using an AC Reference

In applications where the reference has AC-signal com-

ponents, the MAX5302 has multiplying capability within

the reference input range specifications. Figure 11

shows a technique for applying a sine-wave signal to

the reference input where the AC signal is offset before

being applied to REF. The reference voltage must

never be more negative than GND.

The MAX5302’s total harmonic distortion plus noise

(THD+N) is typically less than -77dB (full-scale code),

given a 1Vp-p signal swing and input frequencies up to

25kHz. The typical -3dB frequency is 650kHz, as shown

in the Typical Operating Characteristics graphs.

Table 2. Unipolar Code Table

DAC CONTENTS

MSB

LSB

ANALOG OUTPUT

1111 1111 1111 (0)

+VREF

 4095

 4096

1000 0000 0001 (0)

+VREF

 2049

 4096

1000 0000 0000 (0)

+VREF

 2048

 4096

=

+ VREF

2

0111 1111 1111 (0)

+VREF

 2047

 4096

0000 0000 0001 (0)

0000 0000 0000 (0)

Note: ( ) are for sub-bit.

+VREF

 1

 4096

0V

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

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