MAX5302 Просмотр технического описания (PDF) - Maxim Integrated

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MAX5302

Low-Power, 12-Bit Voltage-Output DAC with Serial Interface

Maxim Integrated 

Low-Power, 12-Bit Voltage-Output DAC

with Serial Interface

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 8, VDD = +5V ±10%, VREF = +2.5V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical val-

ues are at TA = +25°C. Output buffer connected in unity-gain configuration.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

DIYGNITAAMLICINPPEURTFSORMANCE

Voltage Output Slew Rate

SR

0.6

V/µs

Output Settling Time

Output Voltage Swing

Current into FB

To ±1/2LSB, VSTEP = 2.5V

Rail-to-rail (Note 2)

14

µs

0 to VDD

V

0.001 ±0.1 µA

Start-Up Time

20

µs

Digital Feedthrough

CS = VDD, DIN = 100kHz

5

nVs

POWER SUPPLIES

Supply Voltage

Supply Current

Supply Current in Shutdown

VDD

IDD (Note 3)

(Note 3)

4.5

5.5

V

0.28

0.4

mA

4

20

µA

Reference Current in Shutdown

0.001 ±0.5 µA

TIMING CHARACTERISTICS (Figure 6)

SCLK Clock Period

SCLK Pulse Width High

SCLK Pulse Width Low

CS Fall to SCLK Rise Setup Time

SCLK Rise to CS Rise Hold Time

tCP

tCH

tCL

tCSS

tCSH

100

ns

40

ns

40

ns

40

ns

0

ns

DIN Setup Time

DIN Hold Time

SCLK Rise to CS Fall Delay

CS Rise to SCLK Rise Hold Time

CS Pulse Width High

tDS

tDH

tCS0

tCS1

tCSW

40

ns

0

ns

40

ns

40

ns

100

ns

Note 1: Guaranteed from code 11 to code 4095 in unity-gain configuration.

Note 2: Accuracy is better than 1LSB for VOUT = 8mV to (VDD - 100mV), guaranteed by a power-supply rejection test at the end

points.

Note 3: RL = ∞, digital inputs at GND or VDD.

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