MAX5150 Просмотр технического описания (PDF) - Maxim Integrated
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MAX5150 Datasheet PDF : 16 Pages
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Low-Power, Dual, 13-Bit Voltage-Output DACs
with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX5150 (continued)
(VDD = +5V ±10%, VREFA = VREFB = 2.048V, RL = 10kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
at TA= +25°C (OS_ tied to AGND for a gain of +2).)
PARAMETER
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SYMBOL
CONDITIONS
VOH
VOL
ISOURCE = 2mA
ISINK = 2mA
SR
To 1/2LSB of full-scale, VSTEP = 4V
MIN TYP MAX UNITS
VDD - 0.5
V
0.13
0.4
V
0.75
V/µs
16
µs
Output Voltage Swing
Rail-to-rail (Note 2)
0 to VDD
V
OSA or OSB Input Resistance
ROS
24
34
kΩ
Time Required to Exit Shutdown
25
µs
Digital Feedthrough
Digital Crosstalk
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current
Power-Supply Current
in Shutdown
CS = VDD, fDIN = 100kHz, VSCLK = 5Vp-p
VDD
IDD
(Note 3)
IDD (SHDN) (Note 3)
5
nV-s
5
nV-s
4.5
5.5
V
0.5
0.65
mA
2
10
µA
Reference Current in Shutdown
TIMING CHARACTERISTICS
SCLK Clock Period
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise
Setup Time
SCLK Rise to CS Rise Hold Time
SDI Setup Time
SDI Hold Time
SCLK Rise to DOUT
Valid Propagation Delay
tCP
tCH
tCL
tCSS
tCSH
tDS
tDH
tDO1
CLOAD = 200pF
0
100
40
40
40
0
40
0
±1
µA
ns
ns
ns
ns
ns
ns
ns
80
ns
SCLK Fall to DOUT
Valid Propagation Delay
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
tDO2
tCS0
tCS1
tCSW
CLOAD = 200pF
80
ns
10
ns
40
ns
100
ns
Note 1: Accuracy is specified from code 12 to code 8191.
Note 2: Accuracy is better than 1LSB for VOUT_ greater than 6mV and less than VDD - 50mV. Guaranteed by PSRR test at the end
points.
Note 3: Digital inputs are set to either VDD or DGND, code = 0000 hex, RL = ∞.
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