MAX5104 Просмотр технического описания (PDF) - Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

MAX5104

Low-Power, Dual, Voltage-Output, 12-Bit DAC with Serial Interface

Maxim Integrated 

Low-Power, Dual, Voltage-Output, 12-Bit DAC

with Serial Interface

Serial-Data Output

The serial-data output, DOUT, is the internal shift register’s

output. DOUT allows for daisy chaining of devices and

data readback. The MAX5104 can be programmed to

shift data out of DOUT on SCLK’s falling edge (Mode 0)

or on the rising edge (Mode 1). Mode 0 provides a lag

of 16 clock cycles, which maintains compatibility with

SPI/QSPI and MICROWIRE interfaces. In Mode 1, the

output data lags 15.5 clock cycles. On power-up, the

device defaults to Mode 0.

User-Programmable Logic Output

User-programmable logic output (UPO) allows an external

device to be controlled through the serial interface

(Table 1), thereby reducing the number of microcontroller

I/O pins required. On power-up, UPO is low.

+5V/+3V

OS_

REF_

VDD

R

MAX5104

DAC_

R

OUT_

GAIN = +2V/V

AGND

DGND

Figure 9. Unipolar Output Circuit (Rail-to-Rail)

Power-Down Lockout Input

The power-down lockout (PDL) pin disables software

shutdown when low. When in power-down, transitioning

PDL from high to low wakes up the part with the output

set to the state prior to power-down. PDL can also be

used to asynchronously wake up the device.

Daisy-Chaining Devices

Any number of MAX5104s can be daisy-chained by

connecting the DOUT pin of one device to the DIN pin

of the following device in the chain (Figure 7).

Since the MAX5104’s DOUT pin has an internal active

pull-up, the DOUT sink/source capability determines the

time required to discharge/charge a capacitive load.

See the digital output VOH and VOL specifications in the

Electrical Characteristics.

Figure 8 shows an alternate method of connecting several

MAX5104s. In this configuration, the data bus is common

to all devices; data is not shifted through a daisy chain.

More I/O lines are required in this configuration because

a dedicated chip-select input (CS) is required for each IC.

__________Applications Information

+5V/+3V

OS_

REF_

VDD

VOS

R

MAX5104

DAC _

R

OUT_

AGND

DGND

Figure 10. Setting OS_ for Output Offset

Table 2. Unipolar Code Table (Gain = +2)

DAC CONTENTS

MSB

LSB

ANALOG OUTPUT

1111 1111 1111 (0)

+VREF

 4095

 4096

⋅

2

Unipolar Output

Figure 9 shows the MAX5104 configured for unipolar,

rail-to-rail operation with a gain of +2V/V. The MAX5104

can produce a 0 to 4.096V output with a 2.048V reference

(Figure 9). Table 2 lists the unipolar output codes. An

offset to the output can be achieved by connecting a

voltage to OS_, as shown in Figure 10. By applying

VOS_ = -1V, the output values will range between 1V

and (1V + VREF · 2).

Bipolar Output

The MAX5104 can be configured for a bipolar output

(Figure 11). The output voltage is given by the equation

(OS_ = AGND):

1000 0000 0001 (0)

1000 0000 0000 (0)

0111 1111 1111 (0)

0000 0000 0001 (0)

0000 0000 0000 (0)

Note: ( ) are for the sub-bit.

+VREF





2049 

4096 

⋅

2

+VREF





2048 

4096 

⋅ 2 = VREF

+VREF

 2047

 4096

⋅

2

+VREF

 1

 4096

⋅

2

0V

10 ______________________________________________________________________________________

Share Link: