MAX4613E(1998) Просмотр технического описания (PDF) - Maxim Integrated
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MAX4613E Datasheet PDF : 8 Pages
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Quad, SPST Analog Switch
supply; connect V- to GND when operating with a sin-
gle supply. Also, all device types can operate with
unbalanced supplies such as +24V and -5V. VL must
be connected to +5V to be TTL compatible, or to V+ for
CMOS-logic level inputs. The Typical Operating
Characteristics graphs show typical on-resistance with
±20V, ±15V, ±10V, and ±5V supplies. (Switching times
increase by a factor of two or more for operation at ±5V.)
V+
S
D
Overvoltage Protection
Proper power-supply sequencing is recommended
for all CMOS devices. Do not exceed the absolute
maximum ratings because stresses beyond the list-
ed ratings may cause permanent damage to the
devices. Always sequence V+ on first, followed by
VL, V-, and logic inputs. If power-supply sequencing
is not possible, add two small, external signal
diodes in series with supply pins for overvoltage
protection (Figure 1). Adding diodes reduces the
analog signal range to 1V below V+ and 1V above
V-, but low switch resistance and low leakage char-
acteristics are unaffected. Device operation is
unchanged, and the difference between V+ and V-
should not exceed +44V.
Vg
V-
Figure 1. Overvoltage Protection Using External Blocking Diodes
______________________________________________Timing Diagrams/Test Circuits
LOGIC +3V
INPUT
0V
SWITCH
OUTPUT
0V
tf < 20ns
50%
tr < 20ns
tOFF
VOUT
0.8 x VOUT
0.8 x VOUT
tON
LOGIC INPUT WAVEFORM IS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
+5V
+15V
SWITCH
INPUT
VL
D_
V+
S_
IN_
LOGIC
INPUT
+3V
GND
V-
-15V
REPEAT TEST FOR CHANNELS 2, 3, AND 4.
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
MAX4613
RL
VOUT
CL
( ) RL
VOUT = VD
RL + RDS(ON)
LOGIC +3V
INPUT
50%
0V
SWITCH
OUTPUT
SWITCH
OUTPUT
VD
VO1
0V
VD
VO2
0V
tD
0.9VO
+5V
+15V
0.9VO
tD
VD = 10V
VD = 10V
LOGIC
INPUT
VL
D_
D_
IN_
GND
V+
MAX4613
S_
VO1
S_
VO2
RL1
CL1
RL2
V-
CL2
0V
-15V
RL = 1000Ω
CL = 35pF
CL INCLUDES FIXTURE AND STRAY CAPACITANCE. LOGIC 0 INPUT.
Figure 2. Switching Time
Figure 3. Break-Before-Make Test Circuit
6 _______________________________________________________________________________________
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