MAX31865 Просмотр технического описания (PDF) - Maxim Integrated

Номер в каталоге

Компоненты Описание

Список матч

MAX31865

RTD-to-Digital Converter

Maxim Integrated 

MAX31865

RTD-to-Digital Converter

ALWAYS ACTIVE FAULT DETECTION

MONITOR PINS

FAULT DETECTION

EVERY CONVERSION FAULT DETECTION

IS FORCE+,

FORCE2, FORCE-,

N

RTDIN+, RTDIN-,

PINS > VDD OR <

GND

Y

PROTECT PINS AGAINST

±50V

SET BIT D2 OF FAULT

STATUS REGISTER

ADC HALTS UPDATES

CONVERSION

INITIATED

PERFORM

CONVERSION

IS

RTD RESISTANCE

VALUE > HIGH

N

THRESHOLD

REGISTER

Y

SET BIT D7 OF FAULT

STATUS REGISTER

IS

RTD RESISTANCE

VALUE < LOW

N

THRESHOLD

REGISTER

Y

SET BIT D6 OF FAULT

STATUS REGISTER

SET BIT D0 OF RTD DATA

LSB REGISTER

SET BIT D0 OF RTD DATA

LSB REGISTER

MASTER WRITES

100X010Xb TO

CONFIGURATION

REGISTER

MASTER-INITIATED FAULT-DETECTION CYCLE - AUTOMATIC MODE

FORCE-INPUT

SWITCH

REMAINS

CLOSED

100µs

DELAY

IS VREFIN-

>

N

0.85 x VBIAS

Y

SET BIT D5 OF FAULT

STATUS REGISTER

100µs

DELAY

OPEN

FORCE-

INPUT

SWITCH

210µs

DELAY

IS VREFIN-

<

N

0.85 x VBIAS

Y

SET BIT D4 OF FAULT

STATUS REGISTER

END FAULT

DETECTION

CYCLE

SET BIT D0 OF RTD DATA

LSB REGISTER

CONFIGURATION

REGISTER SET TO

100X000Xb TO

FORCE-INPUT

SWITCH

CLOSED

SET BIT D0 OF RTD DATA

LSB REGISTER

N

IS RTDIN-

<

0.85 x VBIAS

100µs

DELAY

Y

SET BIT D3 OF FAULT

STATUS REGISTER

MASTER WRITES

100X100Xb TO

CONFIGURATION

REGISTER

FORCE-INPUT

SWITCH

REMAINS

CLOSED

SET BIT D0 OF RTD DATA

LSB REGISTER

100µs

DELAY

MASTER-INITIATED FAULT-DETECTION CYCLE - MANUAL MODE

IS VREFIN-

>

0.85 x VBIAS

N

100µs

DELAY

OPEN

FORCE-

INPUT

SWITCH

DID

MASTER WRITE

100X110Xb TO

CONFIGURATION

REGISTER

Y

N

SET BIT D5 OF FAULT

STATUS REGISTER

Y 100µs

DELAY

IS VREFIN-

<

N

0.85 x VBIAS

Y

SET BIT D4 OF FAULT

STATUS REGISTER

SET BIT D0 OF RTD DATA

LSB REGISTER

END FAULT

DETECTION

CYCLE

CONFIGURATION

REGISTER SET TO

100X000Xb TO

FORCE-INPUT

SWITCH

CLOSED

SET BIT D0 OF RTD DATA

LSB REGISTER

N

IS RTDIN-

<

0.85 x VBIAS

Y

SET BIT D3 OF FAULT

STATUS REGISTER

100µs

DELAY

SET BIT D0 OF RTD DATA

LSB REGISTER

Figure 4. Fault Detection Flowcharts

Maxim Integrated

  11

Share Link: