MAX17480GTL Просмотр технического описания (PDF) - Maxim Integrated
Номер в каталоге
Компоненты Описание
Список матч
MAX17480GTL Datasheet PDF : 48 Pages
| |||
AMD 2-/3-Output Mobile Serial
VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
DH_ Gate-Driver Source/Sink
Current
IDH_ DH_ forced to 2.5V, BST_ - LX_ forced to 5V
DL_ Gate-Driver Source Current
IDL_ DL_ forced to 2.5V
DL_ Gate-Driver Sink Current
Dead Time
Internal BST1, BST2 Switch RON
IDL_ (SINK)
tDH_DL
tDL_DH
DL_ forced to 2.5V
DH_ low to DL_ high
DL_ low to DH_ high
BST1, BST2 to VDD, IBST1 = IBST2 = 10mA
Internal BST3 Switch RON
2-WIRE I2C BUS LOGIC INTERFACE
BST3 to VDD, IBST3 = 10mA
SVI Logic-Input Current
SVC, SVD, TA = +25°C
SVI Logic-Input Threshold
SVC, SVD, rising edge, hysteresis 0.14 x
VDDIO (V)
SVC Clock Frequency
fSVC
START Condition Hold Time
tHD;STA
Repeated START Condition
Setup Time
tSU;STA
9
9
-1
0.3 x
VDDIO
160
160
STOP Condition Setup Time
Data Hold
tSU;STO
160
tHD;DAT
A master device must internally provide a
hold time of at least 300ns for the SVD
signal (referred to the VIHMIN of SVC signal)
to bridge the undefined region of SVC’s
falling edge
Data Setup Time
tSU;DAT
10
SVC Low Period
tLOW
160
SVC High Period
tHIGH Measured from 10% to 90% of VDDIO
60
SVC/SVD Rise and Fall Time
tR, tF
Input filters on SVD and SVC suppress
noise spike less than 50ns
Pulse Width of Spike Suppression
INPUTS AND OUTPUTS
Logic-Input Current
Logic-Input Levels
SHDN, PGD_IN, TA = +25°C
ILIM3, OPTION, TA = +25°C
SHDN, rising edge, hysteresis = 225mV
-1
-200
0.8
High, OPTION, ILIM3
VCC -
0.4
Input Logic Levels
3.3V, OPTION
2.75
2V, OPTION
1.65
Low, OPTION, ILIM3
PGD_IN Logic-Input Threshold
PGD_IN, rising edge, hysteresis = 65mV
0.3 x
VDDIO
TYP
2.2
2.7
8
20
20
10
10
20
MAX
35
35
20
20
UNITS
A
A
A
ns
+1
0.7 x
VDDIO
3.4
µA
V
MHz
ns
ns
ns
70
ns
ns
ns
ns
40
ns
ns
+1
µA
+200
nA
2.0
V
3.85
V
2.35
0.4
0.7 x
VDDIO
V
6 _______________________________________________________________________________________
Share Link: 