MAX17480 Просмотр технического описания (PDF) - Maxim Integrated
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MAX17480 Datasheet PDF : 48 Pages
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AMD 2-/3-Output Mobile Serial
VID Controller
Pin Description (continued)
PIN
NAME
FUNCTION
33
CSP1
Positive Current-Sense Input for SMPS1. Connect to the positive side of the output current-sensing
resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.
Negative Current-Sense Input for SMPS1. Connect to the negative side of the output current-sensing
34
CSN1 resistor or the filtering capacitor if the DC resistance of the output inductor is utilized for current sensing.
A 20 discharge FET is enabled from CSN1 to PGND when the SMPS1 is shut down.
Feedback Sense Input for SMPS1. Connect a resistor RFBDC1 between FBDC1 and the positive side
of the feedback remote sense, and a capacitor from FBAC1 to couple the AC ripple from FBAC1 to
FBDC1. An integrator on FBDC1 corrects for output ripple and ground-sense offset.
35
FBDC1 To enable a DC load-line less than the AC load-line, add a resistor from FBAC1 to FBDC1.
To enable a DC load-line equal to the AC load-line, short FBAC1 to FBDC1. See the Core Steady-
State Voltage Positioning (DC Droop) section.
FBDC1 is high impedance in shutdown.
Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS1. The RC network between
this pin and the positive side of the remote-sensed output voltage sets the transient AC droop:
36
FBAC1
RDROOP
_
AC1
=
RFBAC1 × RFBDC1
RFBAC1 + RFBDC1 + RFB1
Z CFB1
× RSENSE1 × Gm(FBAC1)
where RDROOP_AC1 is the transient (AC) voltage-positioning slope that provides an acceptable
trade-off between stability and load-transient response, Gm(FBAC1) = 2mS (typ), RSENSE1 is the
value of the current-sense element that is used to provide the (CSP1, CSN1) current-sense voltage,
ZCFB1 is the impedance of CFB1, and FBAC1 is high impedance in shutdown.
SMPS1 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS1
internally connects to a transconductance amplifier that fine tunes the output voltage—
37
GNDS1 compensating for voltage drops from the SMPS ground to the load ground.
Connect GNDS1 or GNDS2 above 0.9V combined-mode operation (unified core). When GNDS1 is
pulled above 0.9V, GNDS2 is used as the remote ground-sense input.
Four-Level Input to Enable Offset and Change Core SMPS Address
38
OPTION
OPTION
VCC
3.3V
2V
GND
OFFSET
ENABLED
0
0
1
1
SMPS1
ADDRESS
BIT 1 (VDD0)
BIT 2 (VDD1)
BIT 1 (VDD0)
BIT 2 (VDD1)
SMPS2
ADDRESS
BIT 2 (VDD1)
BIT 1 (VDD0)
BIT 2 (VDD1)
BIT 1 (VDD0)
When OFFSET is enabled, the MAX17480 enables a fixed +12.5mV offset on SMPS1 and SMPS2
VID codes after PGD_IN goes high. This configuration is intended for applications that implement a
load line. An external resistor at FBDC_ sets the load-line. The offset can be disabled by setting
the PSI_L bit to 0 through the serial interface.
Additionally, the OPTION level also allows core SMPS1 and SMPS2 to take on either the VDD0 or
VDD1 addresses. VDD0 refers to CORE0, and VDD1 refers to CORE1 for the AMD CPU.
The NB SMPS is not affected by the OPTION setting.
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