MAX11626(2014) Просмотр технического описания (PDF) - Maxim Integrated

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MAX11626
(Rev.:2014)

12-Bit, 300ksps ADCs with FIFO and Internal Reference

Maxim Integrated 

MAX11626–MAX11629/

MAX11632/MAX11633

12-Bit, 300ksps ADCs

with FIFO and Internal Reference

Pin Description

MAX11626

MAX11627

(4 CHANNELS)

5, 6, 7

—

—

1–4

MAX11628

MAX11629

(8 CHANNELS)

—

—

1–7

—

—

—

—

8

8

—

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

MAX11632

MAX11633

(16 CHANNELS)

—

1–15

—

—

16

—

—

17

18

NAME

FUNCTION

N.C.

AIN0–AIN14

AIN0–AIN6

AIN0–AIN3

No Connection. Not internally connected.

Analog Inputs

Analog Inputs

Analog Inputs

Active-Low Conversion Start Input/Analog Input 15.

CNVST/AIN15 See Table 3 for details on programming the setup

register.

CNVST/AIN7

Active-Low Conversion Start Input/Analog Input 7.

See Table 3 for details on programming the setup

register.

CNVST

REF

GND

Active-Low Conversion Start Input. See Table 3 for

details on programming the setup register.

Reference Input. Bypass to GND with a 0.1µF

capacitor.

Ground

19

VDD

Power Input. Bypass to GND with a 0.1µF capacitor.

Active-Low Chip-Select Input. When CS is low, the

20

CS

serial interface is enabled. When CS is high, DOUT

is high impedance.

Serial Clock Input. Clocks data in and out of the serial

21

SCLK

interface. (Duty cycle must be 40% to 60%.) See

Table 3 for details on programming the clock mode.

22

DIN

Serial Data Input. DIN data is latched into the serial

interface on the rising edge of SCLK.

Serial Data Output. Data is clocked out on the falling

23

DOUT

edge of SCLK. High impedance when CS is connected

to VDD.

24

EOC

End of Conversion Output. Data is valid after EOC

pulls low.

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