MAX11212(2018) Просмотр технического описания (PDF) - Maxim Integrated

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MAX11212
(Rev.:2018)

18-Bit, Single-Channel, Ultra-Low Power, Delta-Sigma ADC with 2-Wire Serial Interface

Maxim Integrated 

MAX11212

18-Bit, Single-Channel, Ultra-Low Power, Delta-

Sigma ADC with 2-Wire Serial Interface

Data Read Following Every Conversion

The MAX11212 indicates conversion data availability

as well as allows the retrieval of data through the RDY/

DOUT output. The RDY/DOUT output idles at the value

of the last bit read unless a 25th SCLK pulse is provided,

causing RDY/DOUT to idle high. RDY/DOUT is pulled low

when the conversion data is available.

Figure 1 shows the timing diagram for the data read.

Once a low is detected on RDY/DOUT, clock pulses at

SCLK clock out the data. Data is shifted out MSB first

and is in binary two’s complement format. Once all the

data has been shifted out, a 25th SCLK is required to pull

the RDY/DOUT output back to the idle high state. See

Figure 2.

If the data is not read before the next conversion data is

updated, the old data is lost, as the new data overwrites

the old value.

Data Read Followed by Self-Calibration

To initiate self-calibration at the end of a data read, provide

a 26th SCLK pulse. After reading the 16 bits of conversion

data, a 25th positive edge on SCLK pulls the RDY/DOUT

output back high, indicating end of data read. Provide a

26th SCLK pulse to initiate a self-calibration routine start-

ing on the falling edge of the 26th SCLK. A subsequent

falling edge of RDY/DOUT indicates data availability at

the end of calibration. The timing is illustrated in Figure 3.

SCLK

RDY/DOUT

t5

1

t3

t1

t2

2

3

D17

D16

CONVERSION IS DONE

DATA IS AVAILABLE

Figure 1. Timing Diagram for Data Read After Conversion

24

t4

0

t7

t6

CONVERSION IS DONE

DATA IS AVAILABLE

SCLK

1

2

3

RDY/DOUT

CONVERSION IS DONE

DATA IS AVAILABLE

D17

D16

24

0

25

25TH SLK RISING EDGE

PULLS RDY/DOUT

HIGH

CONVERSION IS DONE

DATA IS AVAILABLE

Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK

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