MAX11208AEUB Просмотр технического описания (PDF) - Maxim Integrated

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MAX11208AEUB

20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADC with 2-Wire Serial Interface

Maxim Integrated 

20-Bit, Single-Channel, Ultra-Low-Power,

Delta-Sigma ADC with 2-Wire Serial Interface

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values

are at TA = +25NC under normal conditions, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

SCLK Rising Edge Data Hold

Time

t4

Allows for positive edge data read

3

ns

RDY/DOUT Fall to SCLK Rising

Edge

t5

0

ns

Next Data Update Time; No Read

Allowed

t6

MAX11208A

MAX11208B

155

Fs

169

Data Conversion Time

MAX11208A

t7

MAX11208B

8.6

ms

73

Data Ready Time After Calibration

Starts (CAL + CNV)

t8

MAX11208A

MAX11208B

208.3

ms

256.1

SCLK High After RDY/DOUT Goes

Low to Activate Sleep Mode

MAX11208A

t9

MAX11208B

0

8.6

ms

0

73

Time from RDY/DOUT Low to

SCLK High for Sleep-Mode

Activation

MAX11208A

t10

MAX11208B

0

8.6

ms

0

73

Data Ready Time After Wake-Up

from Sleep Mode

MAX11208A

t11

MAX11208B

8.6

ms

73

Data Ready Time After Calibration

MAX11208A

from Sleep-Mode Wake-Up (CAL

t12

+ CNV)

MAX11208B

208.4

ms

256.2

Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.

Note 3: VAINP = VAINN.

Note 4: ppmFSR is parts per million of full-scale range.

Note 5: Positive full-scale error includes zero-scale errors.

Note 6: The MAX11208A has no normal-mode rejection at 50Hz or 60Hz.

4   _______________________________________________________________________________________

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