L80227 Просмотр технического описания (PDF) - Unspecified

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L80227

10BASE-T/100BASE-TX Ethernet PHY

Unspecified 

Figures

1.1 Top Level Block Diagram

1-2

2.1 L80227 Device Block Diagram

2-4

2.2 100BASE-TX and 10BASE-T Frame Format

2-5

2.3 MII Frame Format

2-6

2.4 TP Output Voltage Template

2-17

2.5 TP Input Voltage Template (10 Mbits/s)

2-19

2.6 Link Pulse Output Voltage Template (10 Mbits/s)

2-23

2.7 NLP vs FLP Link Pulse

2-24

2.8 SOI Output Voltage Template (10 Mbits/s)

2-33

3.1 Device Logic Diagram

3-2

5.1 MI Serial Port Frame Timing Diagram

5-3

5.2 MI Serial Frame Structure

5-4

6.1 25 MHz Output Timing

6-7

6.2 Transmit Timing (100 Mbits/s)

6-9

6.3 Transmit Timing (10 Mbits/s)

6-10

6.4 Receive Timing, Start of Packet (100 Mbits/s)

6-13

6.5 Receive Timing, End of Packet (100 Mbits/s)

6-13

6.6 Receive Timing, Start of Packet (10 Mbits/s)

6-14

6.7 Receive Timing, End of Packet (10 Mbits/s)

6-15

6.8 RX_EN Timing

6-15

6.9 Collision Timing, Receive (100 Mbits/s)

6-17

6.10 Collision Timing, Receive (10 Mbits/s)

6-17

6.11 Collision Timing, Transmit (100 Mbits/s)

6-18

6.12 Collision Timing, Transmit (10 Mbits/s)

6-18

6.13 Collision Test Timing

6-18

6.14 NLP Link Pulse Timing

6-23

6.15 FLP Link Pulse Timing

6-24

6.16 Jabber Timing

6-25

6.17 MI Serial Port Timing

6-26

6.18 L80227 64-Pin LQFP, Top View

6-33

6.19 64-Pin LQFP Package Drawing

6-34

A.1 Typical Network Interface Adapter Card Schematic Using

the L80227

A-2

A.2 Typical Switching Port Schematic Using L80227

A-3

A.3 Typical External PHY Schematic Using L80227

A-4

A.4 MII Output Driver Characteristics

A-10

xi

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