ISP1161 Просмотр технического описания (PDF) - Philips Electronics

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ISP1161

Full-speed Universal Serial Bus single-chip host and device controller

Philips Electronics 

Philips Semiconductors

ISP1161

Full-speed USB single-chip host and device controller

Bits RESET, RESUME, EOT and SOF are cleared upon reading the Interrupt

Register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated

Endpoint Status Register.

Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the

current bus status when reading the Interrupt Register.

SETUP and OUT token interrupts are generated after ISP1161’s DC has

acknowledged the associated data packet. In bulk transfer mode, the ISP1161’s DC

will issue interrupts for every ACK received for an OUT token or transmitted for an IN

token.

In isochronous mode, an interrupt is issued upon each packet transaction. The

firmware must take care of timing synchronization with the host. This can be done via

the Pseudo Start-Of-Frame (PSOF) interrupt, enabled via bit IEPSOF in the Interrupt

Enable Register. If a Start-Of-Frame is lost, PSOF interrupts are generated every

1 ms. This allows the firmware to keep data transfer synchronized with the host. After

3 missed SOF events the ISP1161’s DC will enter ‘suspend’ state.

An alternative way of handling isochronous data transfer is to enable both the SOF

and the PSOF interrupts and disable the interrupt for each isochronous endpoint.

DC Interrupt register

RESET

SUSPND

RESUME

SOF

EP14

...

...

EP0IN

EP0OUT

EOT

IERST

IESUSP

IERESM

IESOF

...

IEP14

...

IEP0IN

IEP0OUT

IEEOT

DC Interrupt Enable register

Fig 22. DC interrupt logic.

...

...

DC Device Mode register

INTENA

PULSE

GENERATOR

DC Hardware Configuration

register

INTLVL

INTPOL

1

0

INT2

MGT946

9397 750 08313

Product data

Rev. 01 — 3 July 2001

© Philips Electronics N.V. 2001. All rights reserved.

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