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ISP1161 Просмотр технического описания (PDF) - Philips Electronics

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ISP1161 Datasheet PDF : 127 Pages
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
microprocessors can read or write ISP1161’s internal control registers and FIFO
buffer RAM through the parallel I/O (PIO) operating mode. Figure 9 shows the parallel
I/O interface between a microprocessor and ISP1161.
D [15:0]
µP bus I/F
D [15:0]
RD
WR
MICRO-
CS
PROCESSOR
A2
A1
IRQ1
IRQ2
RD
WR
CS ISP1161
A1
A0
INT1
INT2
MGT933
Fig 9. Parallel I/O interface between microprocessor and ISP1161.
8.2 DMA mode
ISP1161 also provides DMA mode for external microprocessors to access its internal
FIFO buffer RAM. Data can be transferred by DMA operation between a
microprocessor’s system memory and ISP1161’s internal FIFO buffer RAM. Note: the
DMA operation must be controlled by the external microprocessor system’s DMA
controller (Master). Figure 10 shows the DMA interface between a microprocessor
system and ISP1161. ISP1161 provides two DMA channels: DMA channel 1
(controlled by DREQ1, DACK1 signals) is for the DMA transfer between a
microprocessor’s system memory and ISP1161 HC’s internal FIFO buffer RAM. DMA
channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer between a
microprocessor’s system memory and ISP1161 DC’s internal FIFO buffer RAM. The
EOT signal is an external end-of-transfer signal used to terminate the DMA transfer.
Some microprocessors may not have this signal. In this case, ISP1161 provides an
internal EOT signal to terminate the DMA transfer as well. Setting the
HcDMAConfiguration register (21H - Read, A1H - Write) enables ISP1161’s HC
internal DMA counter for DMA transfer. When the DMA counter reaches the value
that is set in the HcTransferCounter (22H - Read, A2H - Write) register to be used as
the byte count of the DMA transfer, the internal EOT signal will be generated to
terminate the DMA transfer.
9397 750 08313
Product data
Rev. 01 — 3 July 2001
© Philips Electronics N.V. 2001. All rights reserved.
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