IDT74LVCH245APG Просмотр технического описания (PDF) - Integrated Device Technology
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IDT74LVCH245APG
Integrated Device Technology
IDT74LVCH245APG Datasheet PDF : 6 Pages
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IDT74LVCH245A
3.3V CMOS OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
DIR 1
A1
2
A2
3
A3
4
A4
5
A5
6
20
VCC
19
OE
18
B1
17
B2
16
B3
15
B4
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +6.5
V
TSTG Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
IOK
VI < 0 or VO < 0
–50
mA
ICC
Continuous Current through each
ISS
VCC or GND
±100
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
A6
7
14
B5
A7
8
A8
9
GND 10
13
B6
12
B7
11
B8
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance VOUT = 0V
5.5
8
pF
CI/O
I/O Port Capacitance VIN = 0V
6.5
8
pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
OE
DIR
Ax
Bx
Description
Output Enable Input (Active LOW)
Direction Control Input
Data Inputs(1)
Data Outputs
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE(1)
Inputs
OE
DIR
Outputs
L
L
L
H
Bus B Data to Bus A
Bus A Data to Bus B
H
X
Z
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2
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