FCT162511AT Просмотр технического описания (PDF) - Integrated Device Technology
Номер в каталоге
Компоненты Описание
Список матч
FCT162511AT Datasheet PDF : 11 Pages
| |||
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (SET UP TIMES)
Symbol Parameter
tSU Set-up Time
HIGH or LOW
Ax to CLKAB
tSU Set-up Time
PAx to CLKAB
tSU Set-up Time
Bx to CLKBA,
PBx to CLKBA
tSU Set-up Time
Ax to LEAB
tSU Set-up Time
PAx to LEAB
tSU Set-up Time
Bx to LEBA
PBx to LEBA
tSK(O) Output Skew(4)
Test Conditions(1,3)
GEN/CHK LOW PBx valid
CL = 50pF
GEN/CHK HIGH
PBx not valid RL = 500Ω
PERB valid
PERB not valid
GEN/CHK HIGH PERB valid
PERB not valid
PERA valid
PERA not valid
CLKAB LOW
GEN/CHK LOW
CLKAB LOW
GEN/CHK HIGH
CLKAB HIGH
GEN/CHK LOW
CLKAB HIGH
GEN/CHK HIGH
CLKAB LOW
GEN/CHK HIGH
CLKAB HIGH
GEN/CHK HIGH
CLKBA LOW
CLKBA HIGH
PBx valid
PBx not valid
PERB valid
PERB not valid
PBx valid
PBx not valid
PERB valid
PERB not valid
PERB valid
PERB not valid
PERB valid
PERB not valid
PERA valid
PERA not valid
PERA valid
PERA not valid
FCT162511AT
Com'l.
Mil.
Min. Max. Min. Max.
4—4—
3—3—
4—4—
3—3—
4—4—
3—3—
4—4—
3—4—
3.5 — 3.5 —
3—3—
3.5 — 3.5 —
3—3—
3.5 — 3.5 —
3—3—
3.5 — 3.5 —
3—3—
3.5 — 3.5 —
3—3—
3.5 — 3.5 —
3—3—
3.5 — 3.5 —
3—3—
3.5 — 3.5 —
3—3—
— 0.5 — 0.5
FCT162511CT
Com'l.
Mil.
Min. Max. Min. Max. Unit
3 — 3.5 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
3 — 3 — ns
— 0.5 — 0.5 ns
2916 tbl 11
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (HOLD TIMES)
FCT162511AT
FCT162511CT
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition(1) Min. Max. Min. Max. Min. Max. Min. Max. Unit
tH Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA CL = 50pF 1 — 1 — 1 — 1 — ns
tH Hold Time HIGH or LOW PAx to LEAB
RL = 500Ω 1 — 1 — 1 — 1 — ns
tH Hold Time HIGH or LOW PBx to LEBA
1 — 1 — 1 — 1 — ns
tH Hold Time Ax to CLKAB, PAx to CLKAB
1 — 1 — 0 — 0 — ns
tH Hold Time Bx to CLKBA, PBx to CLKBA
tW LEAB or LEBA Pulse Width HIGH(2)
tW CLKAB or CLKBA Pulse Width HIGH or LOW(2)
1 — 1 — 0 — 0 — ns
3 — 3 — 3 — 3 — ns
3 — 3 — 3 — 3 — ns
NOTES:
2916 tbl 12
1. See test circuits and waveforms.
2. This parameter is guaranteed but not tested.
3. "Not valid" means the set-up time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure
proper functioning of the A to B or B to A port respective to the indicated direction.
4. Skew between any two outputs of the same package, switching in the same direction, excluding PERx in clocked mode, and Pxx (parity bits) and
PERx in transparent/latched mode. This parameter is guaranteed by design.
5.11
9
Share Link: 