IDT74FCT162511ATPVG(2009) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT74FCT162511ATPVG
(Rev.:2009)

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY

Integrated Device Technology 

IDT54/74FCT162511AT/CT

FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER

MILITARY AND INDUSTRIAL TEMPERATURE RANGES

SWITCHING CHARACTERISTICS OVER OPERATING RANGE (SET UP TIMES)

Symbol

tSU

tSU

tSU

tSU

tSU

tSU

tSK(O)

Parameter

Set-up Time

HIGH or LOW

Ax to CLKAB

Set-up Time

PAx to CLKAB

Set-up Time

Bx to CLKBA,

PBx to CLKBA

Set-up Time

Ax to LEAB

Set-up Time

PAx to LEAB

Set-up Time

Bx to LEBA

PBx to LEBA

Output Skew(4)

Test Conditions(1, 3)

GEN/CHK LOW

PBx valid

PBx not valid

GEN/CHK HIGH

PERB valid

PERB not valid

GEN/CHK HIGH

PERB valid

PERB not valid

PERA valid

PERA not valid

CLKAB LOW

GEN/CHK LOW

CLKAB LOW

GEN/CHK HIGH

CLKAB HIGH

GEN/CHK LOW

CLKAB HIGH

GEN/CHK HIGH

CLKAB LOW

GEN/CHK HIGH

CLKAB HIGH

GEN/CHK HIGH

CLKBA LOW

CLKBA HIGH

PBx valid

PBx not valid

PERB valid

PERB not valid

PBx valid

PBx not valid

PERB valid

PERB not valid

PERB valid

PERB not valid

PERB valid

PERB not valid

PERA valid

PERA not valid

PERA valid

PERA not valid

CL = 50pF

RL = 500Ω

FCT162511AT

FCT162511CT

Ind.

Mil.

Ind.

Mil.

Min. Max. Min. Max. Min. Max. Min. Max. Unit

4 — 4 — 3 — 3.5 — ns

3 — 3 — 3 — 3 — ns

4 — 4 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

4 — 4 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

4 — 4 — 3 — 3 — ns

3 — 4 — 3 — 3 — ns

3.5 — 3.5 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

3.5 — 3.5 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

3.5 — 3.5 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

3.5 — 3.5 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

3.5 — 3.5 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

3.5 — 3.5 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

3.5 — 3.5 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

3.5 — 3.5 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

— 0.5 — 0.5 — 0.5 — 0.5 ns

SWITCHING CHARACTERISTICS OVER OPERATING RANGE (HOLD TIMES)

Symbol

tH

tH

tH

tH

tH

tW

tW

Parameter

Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA

Hold Time HIGH or LOW PAx to LEAB

Hold Time HIGH or LOW PBx to LEBA

Hold Time Ax to CLKAB, PAx to CLKAB

Hold Time Bx to CLKBA, PBx to CLKBA

LEAB or LEBA Pulse Width HIGH(2)

CLKAB or CLKBA Pulse Width HIGH or LOW(2)

Condition(1)

CL= 50pF

RL = 500Ω

FCT162511AT

FCT162511CT

Ind.

Mil.

Ind.

Mil.

Min. Max. Min. Max. Min. Max. Min. Max. Unit

1 — 1 — 1 — 1 — ns

1 — 1 — 1 — 1 — ns

1 — 1 — 1 — 1 — ns

1 — 1 — 0 — 0 — ns

1 — 1 — 0 — 0 — ns

3 — 3 — 3 — 3 — ns

3 — 3 — 3 — 3 — ns

NOTES:

1. See test circuits and waveforms.

2. This parameter is guaranteed but not tested.

3. "Not valid" means the set-up time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure proper functioning of the

A to B or B to A port respective to the indicated direction.

4. Skew between any two outputs of the same package, switching in the same direction, excluding PERx in clocked mode, and Pxx (parity bits) and PERx in transparent/

latched mode. This parameter is guaranteed by design.

8

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