IDT29FCT520A Просмотр технического описания (PDF) - Integrated Device Technology
Номер в каталоге
Компоненты Описание
Список матч
IDT29FCT520A Datasheet PDF : 8 Pages
| |||
IDT29FCT520A/B/C
MULTILEVEL PIPELINE REGISTER
PIN CONFIGURATIONS
I0 1
24 Vcc
I1 2
23 S0
D0 3
22 S1
D1 4 P24-1, 21 Y0
D2 5 D24-1, 20
D3
6
E24-1
&
19
Y1
Y2
D4 7 SO24-2 18 Y3
D5 8
17 Y4
D6 9
16 Y5
D7 10
15
Y6
CLK 11
14 Y7
GND 12
13 OE
DIP/CERPACK/SOIC
TOP VIEW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
4 3 2 28 27 26
D1 5
1
25 Y0
D2 6
24 Y1
D3 7
23 Y2
NC 8
L28-1
22 NC
D4 9
21 Y3
D5 10
20 Y4
D6 11
19 Y5
12 13 14 15 16 17 18
2620 drw 02
LCC
TOP VIEW
DEFINITION OF FUNCTIONAL TERMS
Pin Names
Description
Dn
Register input port.
CLK
Clock input. Enter data into registers on LOW-
to-HIGH transitions.
I0, I1
Instruction inputs. See Figure 1 and
In-
struction Control Tables.
S0, S1
Multiplexer select. Inputs either register A1, A2,
B1 or B2 data to be available at the output port.
OE
Output enable for 3-state output port
Yn
Register output port.
REGISTER SELECTION
S1
S0
0
0
0
1
1
0
1
1
2620 tbl 01
Register
B2
B1
A2
A1
2620 tbl 02
7.2
2
Share Link: 