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IC61LV256

32K x 8 Hight Speed SRAM with 3.3V

Integrated Circuit Solution Inc 

IC61LV256

WRITE CYCLE NO. 2 (WE Controlled, OE is HIGH During Write Cycle) (1,2)

ADDRESS

OE

t WC

VALID ADDRESS

t HA

CE LOW

WE

DOUT

t SA

DATA UNDEFINED

t AW

t PWE1

t HZWE

DIN

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

WRITE CYCLE NO. 3 (WE Controlled, OE is LOW During Write Cycle) (1)

ADDRESS

OE LOW

t WC

VALID ADDRESS

t HA

CE LOW

WE

DOUT

t SA

DATA UNDEFINED

DIN

t AW

t PWE2

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

Notes:

1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if OE > VIH.

8

Integrated Circuit Solution Inc.

AHSR027-0B 11/28/2003

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