IC61LV256 Просмотр технического описания (PDF) - Integrated Circuit Solution Inc

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IC61LV256

32K x 8 Hight Speed SRAM with 3.3V

Integrated Circuit Solution Inc 

IC61LV256

WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)

Symbol Parameter

tWC Write Cycle Time

tSCE CE to Write End

tAW Address Setup Time

to Write End

tHA Address Hold

from Write End

tSA Address Setup Time

tPWE(4) WE Pulse Width

tSD Data Setup to Write End

tHD Data Hold from Write End

tHZWE(3) WE LOW to High-Z Output

tLZWE(3) WE HIGH to Low-Z Output

-8 ns

-10 ns

-12 ns

-15 ns

Min. Max. Min. Max. Min. Max. Min. Max. Unit

8 — 10 — 12 — 15 — ns

7 — 8 — 8 — 10 — ns

7 — 8 — 8 — 10 — ns

0 — 0 — 0 — 0 — ns

0 — 0 — 0 — 0 — ns

7 — 10 — 12 — 15 — ns

4.5 — 5 — 6 — 7 — ns

0 — 0 — 0 — 0 — ns

— 3.5 — 4 — 6 — 7 ns

0 — 0 — 0 — 0 — ns

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse

levels of 0 to 3.0V and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid

states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold

timing are referenced to the rising or falling edge of the signal that terminates the Write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%

tested.

4. Tested with OE HIGH.

AC WAVEFORMS

WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 )

t WC

ADDRESS

CE

WE

DOUT

DIN

VALID ADDRESS

t SA

t SCE

t HA

DATA UNDEFINED

t AW

t PWE1

t PWE2

t HZWE

HIGH-Z

t LZWE

t SD

t HD

DATAIN VALID

Integrated Circuit Solution Inc.

7

AHSR027-0B 11/28/2003

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