CY7C43686AV-10AI Просмотр технического описания (PDF) - Cypress Semiconductor
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CY7C43686AV-10AI Datasheet PDF : 40 Pages
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CY7C43646AV
CY7C43666AV
CY7C43686AV
Pin Definitions (continued)
Signal Name Description I/O
Function
FFA/IRA
Port A Full/Input
Ready Flag
O This is a dual-function pin. In the CY Standard mode, the FFA function is selected.
FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA
function is selected. IRA indicates whether or not there is space available for writing to
the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
FFC/IRC
Port C Full/Input
Ready Flag
O This is a dual-function pin. In the CY Standard mode, the FFC function is selected.
FFC indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRC
function is selected. IRC indicates whether or not there is space available for writing to
the FIFO2 memory. FFC/IRC is synchronized to the LOW-to-HIGH transition of CLKC.
FS1/SEN
FS0/SD
Flag Offset
Select 1/Serial
Enable
Flag Offset
Select 0/Serial
Data
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register
programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select
the flag offset programming method. Three offset register programming methods are
I
available: automatically load one of three preset values (8, 16, or 64), parallel load from
Port A, and serial load. When serial load is selected for flag offset register programming,
FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into
the X and Y registers. The number of bit Writes required to program the offset registers
is 40 for the CY7C43646AV, 48 for the CY7C43666AV, and 56 for the CY7C43686AV.
The first bit Write stores the Y-register MSB and the last bit Write stores the X-register
LSB.
MBA
Port A Mailbox
Select
I A HIGH level on MBA chooses a mailbox register for Read or Write operation on Port
A. When a Read operation is performed on Port A, a HIGH level on MBA selects data
from the Mail2 register for output and a LOW level selects FIFO2 output register data
for output. When writing data into Port A, a HIGH level on MBA will write the data into
Mail1 register and a LOW will write into FIFO1.
MBB
Port B Mailbox
Select
I When a Read operation is performed on Port B, a HIGH level on MBB selects data
from the Mail1 register for output and a LOW level selects FIFO1 output register data
for output.
MBC
Port C Mailbox
Select
I When writing data into Port C, a HIGH level on MBC will write the data into Mail2
register and a LOW will write into FIFO2.
MBF1
Mail1 Register
Flag
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH
by a LOW-to-HIGH transition of CLKB when a Port B Read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2
Mail2 Register
Flag
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH
by a LOW-to-HIGH transition of CLKA when a Port A Read is selected and MBA is HIGH.
MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
MRS1
FIFO1 Master
Reset
I A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1
selects the programming method (serial or parallel) and one of three programmable flag
default offsets for FIFO1. It also configures Port B for bus size and endian arrangement.
Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while MRS1 is LOW.
MRS2
FIFO2 Master
Reset
I A LOW on this pin initializes the FIFO2 Read and Write pointers to the first location
of memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2
selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH
transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2
is LOW.
PRS1
FIFO1 Partial
Reset
I A LOW on this pin initializes the FIFO1 Read and Write pointers to the first location
of memory and sets the Port B output register to all zeroes. During Partial Reset,
the currently selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained.
Document #: 38-06026 Rev. *C
Page 5 of 40
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