CS7654 Просмотр технического описания (PDF) - Cirrus Logic

Номер в каталоге

Компоненты Описание

производитель

CS7654

CCD Color-Space Processor with Analog Output

Cirrus Logic 

CS7654

or reading only to CS7654 registers are not put in

the queue but are executed immediately without af-

fecting any transactions occurring on the master

I2C interface.

Any attempt by the external I2C controller to write

to the CS7654 registers while the CS7654 is busy

initializing from an external EEPROM will be ig-

nored. However, reads from the CS7654 are al-

lowed during this time.

If, during a READ or WRITE operation to a slave

device, the CS7654 fails to receive an acknowledge

bit the execution of the command is aborted and the

NODEV bit in the status register is set high. This

bit remains set unless it is explicitly cleared by

writing to it or a new command is written to

CS7654.

Byte Sequence WRITE Format Packet Detail

First Byte

Station Address of CS7654 with LSB

Set LOW

Second Byte Station Address of target slave

device with LSB Set LOW

Third Byte

Device Register Address (0..255)

Fourth Byte

Register Data (0..255)

Table 9. Four-byte WRITE Format Packet

Read Operations in Four-Byte Mode

The READ operation in four-byte mode first re-

quires a three-byte READ-TRIGGER packet to the

CS7654. The first byte is the station address of the

CS7654 with the LSB set LOW. The second byte is

the target slave device’s station address with the

LSB (data direction bit) set HIGH. The third byte is

the register address (0..255).

Byte Sequence READ-TRIGGER format Packet

Details

First Byte

CS7654 Station Address with LSB

Set LOW

Second Byte Target device Station Address with

LSB Set HIGH

Third Byte

Device Register Address (0..255)

Table 10. READ-TRIGGER packet in four-byte mode

The READ-TRIGGER packet initiates a READ

operation by the CS7654 from the target slave de-

vice on the secondary I2C bus. The status register

in the CS7654 may be checked to see if the read op-

eration has been completed. The I2CBUSY bit in

status register 01h at SA 0x34h is set to zero when

the operation is completed.

On completion of a read cycle from the target de-

vice, the CS7654 places the data read into the Slave

Data Hold register at address 19h at SA 0x34h. The

external controller can read this data through the

primary I2C port. This requires first performing an

ADDRESS SET operation to set the address to 19h

at SA 0x34h and then sending a one-byte station

address indicating read to the CS7654. The data

from register 19h at SA 0x34h is then returned by

the CS7654.

Byte Sequence WRITE Format Packet Detail

First Byte

Station Address of CS7654 with

LSB Set LOW

Second Byte Station Address of CS7654 with

LSB Set LOW

Third Byte

Slave Data Hold reg. address 19h

Table 11. Address Set for Slave Data Hold register in

Four-byte mode

Byte Sequence READ Format Packet Details

First Byte

CS7654 Station Address with LSB

set HIGH.

Second Byte Returned data from register 19h of

CS7654

Table 12. READ Format Packet.

Initializing Slave Devices on Secondary I2C

bus from an EPROM

An EPROM may be attached to the secondary I2C

bus for initialization purposes. Resetting the

CS7654 initiates a download of register values

from the EPROM into any of the slave devices on

the secondary I2C bus. The EPROM is assumed to

be at station address A0h. If during initialization,

the CS7654 does not receive an acknowledge bit

from the EPROM, all transactions with the

27

Share Link: