CS7654 Просмотр технического описания (PDF) - Cirrus Logic

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CS7654

CCD Color-Space Processor with Analog Output

Cirrus Logic 

CS7654

CLKIN2X Input Timing

The CLKIN2X, pin 59, will always require a pri-

mary pixel rate clock source. CCD manufacturers

generally specify a pixel clock frequency that is

compatible with one of the analog encoders that

can be used with a given imager. If the analog out-

put is used, the clock frequency input must be

matched precisely. However, digital display sys-

tems, such as those based on VGA graphics adapter

cards and Zoom Video systems, are generally not

sensitive to pixel clock frequency, and will tolerate

a wide range of pixel and frame rates.

Specific pixel-rate clock frequencies for analog en-

coders include 14.31818 MHz for 768H imagers,

the primary ITU-601 13.5 MHz for 720H imagers,

and down to 12.272727 MHz clock rates for 640H

VGA format imagers.

CLKOUT_GRG

CLKOUT_GRG follows the output data rate The

clock output is at 2x the output luma sample rate,

there is no non-interlaced digital output on the

CS7654.

Mode

000

001

010

011

100

101

110

111

CCD Format

CCD

512x480

512x480

512x576

362x480

362x480

362x576

512x576

512x480

512x576

CCD Clock (MHz)

½ input clock

9.818

9.346

9.281

6.75

6.75

6.75

9.563

9.000

9.000

Output Format

same as CCD

640x480

720x480

720x480

640x480

720x480

720x576

720x576

720x480

720x576

Input Clock (MHz)

(30 MHz max.)

24.5454

27.000

27.000

24.5454

27.000

27.000

27.000

27.000

27.000

Table 2. Default Scaling Modes (Register 04h at SA34h)

Scaling Ratio

1:1

4:5

9:13

11:16

11:20

1:2

17:24

2:3

12

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