CDB6420 Просмотр технического описания (PDF) - Cirrus Logic

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CDB6420

Full-Duplex Speakerphone Chip

Cirrus Logic 

CDB6420

Figure 5. CS6420 Connection Diagram

using APO_IN as an input. This connects the sig-

nal path appropriately. The control bit in the soft-

ware (Mic) must be set to APO as well. When

using MICIN as the acoustic side input source,

HDR1 must be in the PREAMP ON (3-4) position,

and the Mic bit in the software should be set to API.

The test loops labeled API and APO are provided to

allow easy probing of the pins of the same name. The

maximum signal present at APO should be 2.8 Vpp

with TGain (see the Software section) set to 0 dB.

Parallel Port Interface

Figure 6 shows the parallel port interface of the

CDB6420 that connects to a PC’s parallel port. The

74HCT541 buffer serves to protect the CS6420

from any damaging surges. The buffer is socketed

for easy replacement. Four of the parallel port data

lines are used to control the microcontroller interface

pins of the CS6420. The RC network serves to min-

imize the ringing common to HCT devices. Test

loops are provided for easy oscilloscope access.

Figure 7. Grounds

DS205DB1

43

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